Time-slot interchange switches having automatic frame alignment measurement and programming capability
OwnerDave MacAdam, Alex Goldhammerinventors
Life of this patent
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Abstract
Time-slot interchange switches include measurement circuits that automatically measure frame alignment associated with a plurality of multi-frame data streams received by the switch. Internal programming circuits are also provided to convert the frame alignment measurements into frame offsets. Unacceptable frame offsets are also automatically identified using error control circuitry. These measurement and programming circuits streamline frame offset measurement techniques and enable on-chip measurement and conversion of frame delays to frame offsets and programming of frame offset registers (FORs).
Claims26
A time-slot interchange switch, comprising:
- an internal frame alignment measurement and programming circuit that determines and stores a first frame offset associated with a first multi-frame data stream received by said switch in a frame offset register, and at least temporarily retains data that identifies presence of an unacceptable frame offset in the internal frame offset register.
A time-slot interchange switch, comprising:
- an internal frame alignment measurement and programming circuit that determines and then stores a plurality of acceptable frame offsets associated with a first plurality of multi-frame data streams received by said switch and determines and then stores an unacceptable frame offset associated with a multi-frame data stream having an offset that exceeds a maximum offset rating of said switch.
A time-slot interchange switch, comprising:
- a first storage device that is disposed internal to said switch and retains frame delay/offset bytes, with each of the frame offset/delay bytes identifying a frame delay or frame offset associated with a respective multi-frame data stream received by said switch;
- and
- a second storage device that is disposed internal to said switch and at least temporarily retains data that identifies presence of an unacceptable frame delay/offset within said first storage device.
A time-slot interchange switch, comprising:
- a frame alignment counter that determines a respective frame delay for each of a plurality of multi-frame data streams received by said switch and generates an error signal if any of the frame delays is excessive;
- a frame delay conversion circuit that converts the frame delays to acceptable frame offsets;
- an error control circuit that generates an error code and an unacceptable frame offset and is responsive to the error signal;
- a temporary register that stores the acceptable frame offsets and the unacceptable frame offset received from said frame delay conversion circuit and said error control circuit, respectively;
- a frame offset register
- a control circuit that writes the acceptable frame offsets and the unacceptable frame offset from said temporary register to a row within said frame offset register;
- and
- an error control register that stores the error code.
A time slot interchange switch, comprising:
- an internal frame alignment measurement circuit that determines a first frame offset associated with a first multi-frame data stream received by said switch;
- an internal frame offset register that retains the first frame offset at a first location therein;
- and
- an internal error code register that retains a pointer having a value that indicates whether an unacceptable frame offset is present in said internal frame offset register.
A method of operating a time slot interchange switch, comprising the steps of:
- measuring a first frame offset associated with a first multi-frame data stream received by the switch and then storing the measured first frame offset as an acceptable or unacceptable frame offset in a frame offset register;
- and
- generating, internal to the switch, user accessible data that identifies presence of an unacceptable frame offset in the frame offset register.
Dependencies are inferred from the claim text.