Semiconductor memory and method for operating the semiconductor memory
AssigneeInfineon Technologies AG
InventorsAlexander Benedix, Kazimierz Szczypinski, Helmut Fischer, Johann Pfeiffer
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Abstract
A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.
Claims14
A semiconductor memory, comprising:
- a clock input for receiving a clock signal;
- a data output for outputting data to be read;
- a signal input for receiving a control signal, the control signal initiating a read-out of the data in a manner dependent on a predetermined signal state of the control signal, a latency elapsing between the predetermined signal state of said signal input and an availability of the data to be read at said data output;
- a measuring device for determining a frequency-dependent characteristic of the clock signal, said measuring device connected to said clock input;
- and
- a control circuit for controlling the latency in a manner dependent on the frequency-dependent characteristic, said control circuit connected to said data output.
A method for operating memories, which comprises the steps of:
- providing a semiconductor memory having a clock input, a signal input, a data output, a measuring device and a control circuit;
- feeding a clock signal to the clock input;
- using the measuring device for determining a value for a latency of the semiconductor memory in a manner dependent on the clock signal;
- using the control circuit to configure the semiconductor memory taking into account the value of the latency;
- feeding a control signal to the signal input for initiating a reading out of data from the semiconductor memory in a manner dependent on a predetermined signal state of the control signal, and the latency elapsing between an availability of the predetermined signal state of the signal input and the availability of the data to be read at the data output;
- and
- reading the data at the data output.
Dependencies are inferred from the claim text.