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US 2002/0176315 A1Published application
Synchronous mirror delay with reduced delay line taps
AssigneeMicron Technology, Inc.
InventorScott Van De Graaff
Life of this patent
Estimating the term…
Abstract
A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non-variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.
Claims131
An SMD circuit comprising:
- a clock source;
- a delay segment coupled to the clock source;
- a data path model coupled to the delay segment;
- a forward delay line coupled to the data path model;
- an SMD control circuit coupled to the forward delay line and coupled to the clock source;
- and
- a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
4 more elements
An SMD circuit comprising:
- a clock source;
- a data path model coupled to the clock source;
- a first delay segment coupled to the data path model;
- a forward delay line coupled to the first delay segment;
- an SMD control circuit coupled to the forward delay line and to the clock source;
- and
- a backward delay line coupled to the clock source, the SMD control circuit, and coupled to a second delay segment.
4 more elements
An integrated circuit comprising:
- a clock input buffer coupled to receive a clock signal with a time period;
- a delay segment coupled to the clock input buffer;
- a data path model coupled to the delay segment;
- a forward delay line coupled to the data path model;
- an SMD control circuit coupled to the forward delay line and to the clock input buffer;
- and
- a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
4 more elements
An integrated circuit comprising:
- a clock input buffer coupled to receive a clock signal with a time period;
- a data path model coupled to the clock input buffer;
- a first delay segment coupled to the data path model;
- a forward delay line coupled to the first delay segment;
- an SMD control circuit coupled to the forward delay line and to the clock input buffer;
- and
- a backward delay line coupled to the SMD control circuit, the clock input buffer, and to a second delay segment.
4 more elements
A memory device comprising:
- an address interface;
- a data interface;
- a control interface;
- and
- an SMD clock recovery and skew adjustment circuit comprising,
- a clock source,
- a delay segment coupled to the clock source,
- a data path model coupled to the delay segment,
- a forward delay line coupled to the data path model,
- an SMD control circuit coupled to the forward delay line and coupled to the clock source, and
- a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
8 more elements
A memory device comprising:
- an address interface;
- a data interface;
- a control interface;
- and
- a SMD clock recovery and skew adjustment circuit comprising,
- a clock input buffer coupled to receive a clock signal,
- a data path model coupled to the clock input buffer,
- a first delay segment coupled to the data path model,
- a forward delay line coupled to the first delay segment,
- an SMD control circuit coupled to the forward delay line and to the clock input buffer, and
- a backward delay line coupled to the SMD control circuit, the clock input buffer, and to a second delay segment.
8 more elements
A DDR memory device interface circuit comprising:
- a data interface;
- a DQS signal interface;
- a data latch coupled to the data interface;
- and
- an SMD clock recovery and skew adjustment circuit coupled to the data latch and coupled to the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises,
- a clock input buffer coupled to receive a clock signal with a time period,
- a data path model coupled to the clock input buffer,
- a first delay segment coupled to the data path model,
- a forward delay line coupled to the first delay segment,
- an SMD control circuit coupled to the forward delay line and to the clock input buffer, and
- a backward delay line coupled to the SMD control circuit, the clock input buffer, and to a second delay segment.
8 more elements
A DDR memory device interface circuit comprising:
- a data interface;
- a DQS signal interface;
- a data latch coupled to the data interface;
- and
- an SMD clock recovery and skew adjustment circuit coupled to the data latch and the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises,
- a clock source,
- a delay segment coupled to the clock source,
- a data path model coupled to the delay segment,
- a forward delay line coupled to the data path model,
- an SMD control circuit coupled to the forward delay line and coupled to the clock source, and
- a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
8 more elements
A method of synchronizing with a clock signal comprising:
- receiving a clock signal having a clock signal time period;
- subtracting a first time period equivalent to a real data path;
- subtracting a second time period that is a static component;
- measuring a remaining component of the clock signal time period;
- reproducing the remaining component of the clock signal time period;
- and
- adding a third time period that is identical to the second time period to the reproduced remaining component of the clock signal time period.
4 more elements
A method of synchronizing with a clock signal comprising:
- receiving a clock signal having sequential first and second clock signal time periods;
- delaying the first clock signal time period a first time delay;
- delaying the first clock signal time period a second time delay equal to a real data path;
- measuring a remaining component of the first clock signal time period;
- delaying the second clock signal time period the first time delay;
- reproducing the remaining component of the first clock signal time period;
- and
- merging the reproduced remaining component of the clock signal time period to the delayed second clock signal time period.
5 more elements
A method of synchronizing with a clock signal comprising:
- coupling a delay segment to a clock source;
- coupling a data path model to the delay segment;
- coupling a forward delay line to the data path model;
- coupling an SMD control circuit to the forward delay line and to the clock source;
- and
- coupling a backward delay line to the SMD control circuit and to the delay segment.
3 more elements
A method of synchronizing with a clock source comprising:
- coupling a data path model to a clock source;
- coupling a first delay segment to the data path model;
- coupling a forward delay line to the first delay segment;
- coupling an SMD control circuit to the forward delay line and to the clock source;
- and
- coupling a backward delay line to the SMD control circuit and to a second delay segment.
3 more elements
A method of synchronizing a memory device with a clock signal comprising:
- forming an address interface;
- forming a data interface;
- forming a control interface;
- and
- forming an SMD clock recovery and skew adjustment circuit comprising,
- coupling a delay segment to a clock source,
- coupling a data path model to the delay segment,
- coupling a forward delay line to the data path model,
- coupling an SMD control circuit to the forward delay line and to the clock source, and
- coupling a backward delay line to the SMD control circuit and to the delay segment.
7 more elements
A method of synchronizing a memory device with a clock source comprising:
- forming an address interface;
- forming a data interface;
- forming a control interface;
- and
- forming an SMD clock recovery and skew adjustment circuit comprising,
- coupling a clock input buffer to receive a clock signal,
- coupling a data path model to the clock input buffer,
- coupling a first delay segment to the data path model,
- coupling a forward delay line to the first delay segment,
- coupling an SMD control circuit to the forward delay line and to the clock input buffer, and
- coupling a backward delay line to the SMD control circuit and to a second delay segment.
8 more elements
A method for synchronizing a DDR memory device interface circuit with a clock signal comprising:
- forming a data interface;
- forming a DQS signal interface;
- forming a data latch coupled to the data interface;
- and
- forming an SMD clock recovery and sketch adjustment circuit coupled to the data latch and the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises,
- a clock input buffer coupled to receive a clock signal,
- a data path model coupled to the clock input buffer,
- a first delay segment coupled to the data path model,
- a forward delay line coupled to the first delay segment,
- an SMD control circuit coupled to the forward delay line and to the clock input buffer, and
- a backward delay line coupled to the SMD control circuit and coupled to a second delay segment.
8 more elements
A method for synchronizing a DDR memory device interface circuit with a clock source comprising:
- forming a data interface;
- forming a DQS signal interface;
- forming a data latch coupled to the data interface;
- and
- forming an SMD clock recovery and skew adjustment circuit coupled to the data latch and the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises,
- a clock source,
- a delay segment coupled to the clock source,
- a data path model coupled to the delay segment,
- a forward delay line coupled to the data path model,
- an SMD control circuit coupled to the forward delay line and to the clock source, and
- a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
8 more elements
Dependencies are inferred from the claim text.