US 2002/0176309 A1 · Controlling output current in rambus DRAM

Abstract

Disclosed is a circuit for controlling output currents of the data ports in a Rambus DRAM having two data ports DQA and DQB. The disclosed circuit arrangements save power and require less chip ‘real estate’ than do known circuit arrangements. First and second current evaluation means output first and second control signals respectively by evaluating currents of the data ports DQA and DQB. A current control value producing means produces a next current control value for the data port DQA by receiving the first control signal and a present current control value of the data port DQA and producing another next current control value for the data port DQB by receiving the second control signal and a present current control value of the data port DQB. The current control value producing means repeats the process to produce the next current control values alternately, and first and second control value latch means for latching the respective current control values of the data ports DQA and DQB produced by the current control value producing means.

Claims19

Dependent claims

In a Rambus DRAM having two data ports DQA and DQB, a circuit for controlling output currents of the data ports, comprising:

first and second current evaluation means for outputting first and second control signals respectively by evaluating currents of the data ports DQA and DQB;
a current control value producing means for producing a next current control value for the data port DQA by receiving the first control signal and a present current control value of the data port DQA and producing a next current control value for the data port DQB by receiving the second control signal and a present current control value of the data port DQB, the current control value producing means operating repetitively to produce the next current control values alternately;
and
first and second control value latch means for latching the respective current control values of the data ports DQA and DQB produced by the current control value producing means.

1 more element

In an output current control circuit in a Rambus DRAM operated by responding to an enabling signal becoming active when a ‘current control command’ is applied to the Rambus DRAM from a controller, a circuit for controlling output current in the Rambus DRAM, comprising:

a first current detector producing a detection signal attained by comparing current flows received from first and second terminals of a first data port by the enabling signal to a predetermined target value;
a second current detector producing a detection signal attained by comparing current flows received from first and second terminals of a second data port by the enabling signal to a predetermined target value;
a first multiplexer selecting one of the signals received from the first and second current detectors by a first control signal and outputting the selected signal;
a second multiplexer selecting one of first and second output current control signals by the first control signal and outputting the selected output current control signal;
an output current control counter producing a signal incremented or decremented by ‘1 bit’ from the signal received from the second multiplexer by the signal received from the first multiplexer;
a first output current latch counter latching the signal received from the output current control counter by a second control signal and producing the latched signal as the first output current control signal;
and
a second output current latch counter latching the signal received from the output current control counter by a third control signal and producing the latched signal as the second output current control signal.

5 more elements

Dependencies are inferred from the claim text.

Controlling output current in rambus DRAM

Life of this patent

Controlling output current in rambus DRAM

Life of this patent

Abstract

Claims19