Bank control circuit in rambus DRAM and semiconductor memory device thereof
AssigneeHynix Semiconductor Inc.
InventorsTae Hyung Jung, Kyung Duk Kim
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Abstract
A semiconductor memory device for performing a dependent bank operation comprises a plurality of banks consisting of memory cells; a plurality of address latch circuits, shared by two adjacent banks respectively, for receiving global address signals and latching local address signals of the selected bank; and a plurality of control circuits, shared by two adjacent banks respectively, for generating control signals and determining the specific bank that is to be activated.
Claims11
A semiconductor memory device wherein a dependent bank operation is performed, comprising:
- a plurality of banks including memory cells;
- and
- a plurality of address latch circuits shared by two adjacent banks respectively, for receiving global address signals and latching local address signals.
A Rambus dynamic random access memory device comprising:
- a plurality of memory bank units for storing data;
- a plurality of sense amp units, disposed on an upper and a lower part of each memory bank, for sensing data in write and read operations;
- a plurality of sense amp driver units for controlling operations of each sense amp unit;
- and
- a plurality of main word line and sub word line driver units for driving word lines and sub word lines of each memory bank,
- wherein the device further comprises a plurality of control units and address latch units, one being shared by two memory banks, for receiving control signals and global address signals and for generating signals to control three sense amp driver units, two main word line and sub word line driver units and bit lines disposed in the two memory banks.
A Rambus dynamic random access device comprising:
- a plurality of memory bank units for storing data;
- a plurality of sense amp units, disposed on an upper and a lower part of each memory bank unit, for sensing data in write and read operations;
- and
- a plurality of sense amp driver units for controlling operations of each sense amp unit,
- wherein the device further comprises a plurality of main word line and sub word line driver units, one being shared by two memory bank units, for driving word lines and sub word lines in each memory bank unit and a plurality of control units and address latch units, one being shared by two memory bank units, for receiving active signals, precharge signals and global address signals and for generating signals to control three sense amp driver units, one main word line and sub word line driver unit and bit lines arranged in the two memory banks.
Dependencies are inferred from the claim text.