Semiconductor memory and method of testing semiconductor memory

A semiconductor memory comprising:

• a memory cell array in which memory cells are arrayed in a matrix;
• a plurality of word lines provided within the memory cell array, each of the word lines connected to a same number of the memory cells in a row direction;
• a word line selection circuit including an input terminal connected to a row selection line for selecting a row and configured to select a predetermined word line among from the plurality of word lines;
• a plurality of memory cell electric power source lines arrayed in the row direction of the memory cell array;
• a row decoder configured to output a selection signal for selecting the row selection line based on a row addressing signal;
• first and second electric power source terminals configured to be mutually independent;
• and
• electric power source switching circuits respectively provided to either end of the memory cell electric power source lines and configured to supply electric power from the first electric power source terminal to the memory cells of the rows to be tested and to supply electric power from the second electric power source terminal to the memory cells except the memory cells of the rows to be tested in the test mode.

A method of testing a semiconductor memory, the method comprising:

• sequentially selecting memory cell electric power source lines of rows to be tested from a plurality of memory cell electric power source lines arrayed in the row direction of a memory cell array in which memory cells are arrayed in a matrix;
• supplying leak testing electric power from a first electric power source terminal to the memory cells of the selected rows to be tested and supplying electric power from a second electric power line to the memory cells of the rows except the rows to be tested;
• and
• measuring a leakage current value of the rows to be tested in order to detect a row including a memory cell where the leakage current is occurring.