Two stage low voltage ferroelectric boost circuit
AssigneeRamtron International Corporation
InventorGary Moscaluk
Life of this patent
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Abstract
A low voltage boost circuit suitable for use in a ferroelectric memory is realized implementing five N-channel devices and two ferroelectric capacitors. The voltage on a word line is boosted using charge sharing techniques in order to assure proper operation at lower power supply voltage conditions. In operation, the gate of an N-channel pass gate is boosted to supply a full VDD voltage on the bottom electrode of a ferroelectric capacitor, which capacitively couples into the word line for an efficient word line voltage boost.
Claims20
A boost circuit for boosting an output node voltage comprising:
- a first transistor having a current path coupled between a first node and a second node, and a gate coupled to a third node;
- a second transistor having a current path coupled between a fourth node and the third node, and a gate coupled to the output node;
- a third transistor having a current path coupled between the third node and ground, and a gate coupled to a fifth node;
- a fourth transistor having a current path coupled between a sixth node and a seventh node, and a gate coupled to the output node;
- a fifth transistor having a current path coupled between the seventh node and ground, and a gate coupled to the fifth node;
- a first capacitor coupled between the second node and the output node;
- and
- a second capacitor coupled between the third node and the seventh node,
- wherein the first, fourth, fifth, and sixth nodes receive control signals.
A boost circuit for boosting an output node comprising:
- a first stage boost control circuit;
- a precharge control circuit coupled to the boost control circuit;
- and
- a second stage boost control circuit coupled to the first stage boost control circuit, to the precharge control circuit, and to an output node.
Dependencies are inferred from the claim text.