Device and method for repairing a memory array by storing each bit in multiple memory cells in the array

A semiconductor device having a memory system including:

• at least one dynamic memory array comprising:
• at least two pairs of complementary digit lines;
• at least two alternating even and odd word lines;
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the at least two alternating even and odd word lines and an access terminal coupled to one of the at least two pairs of complementary digit lines;
• address buffers for receiving memory addresses and outputting corresponding row and column addresses;
• row decoder circuitry coupled to the dynamic memory array and the address buffers for energizing at least two word lines in the dynamic memory array in accordance with each corresponding row address, the row decoder circuitry comprising:
• refresh enable circuitry configurable to output an even row decoder enabling signal and an odd row decoder enabling signal;
• an even row decoder coupled to the refresh enable circuitry, the dynamic memory array, and the address buffers, and enable in response to the even row decoder enabling signal to energize one or more even word lines in the dynamic memory array in accordance with each corresponding row address;
• and
• an odd row decoder coupled to the refresh enable circuitry, the dynamic memory array, and the address buffers and enable in response to the odd row decoder enabling signal to energize one or more odd word lines in the dynamic memory array in accordance with each corresponding row address;
• a column decoder coupled to the address buffers for outputting corresponding row and column addresses;
• sense amplifier and input/output gating circuitry coupled to the column decoder and the dynamic memory array for selecting a pair of the at least two pairs of complementary digit lines in the dynamic memory array in accordance with each column select signal in order to access two or more memory cells in the dynamic memory array each coupled to one of the selected digit lines of the at least two pairs of complementary digit lines and one of the at least two energized word lines;
• and
• a data buffer coupled to the sense amplifier and input/output gating circuitry for communication between the accessed memory cells and external circuitry.

A semiconductor device having at least one memory system comprising:

• at least one dynamic memory array comprising:
• at least two pairs of complementary digit lines;
• at least two odd word lines;
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the at least two odd word lines and an access terminal coupled to one of the at least two pairs of complementary digit lines;
• address buffers for receiving multiplexed memory addresses in the form of a first plurality of address bits followed in time by a second plurality of address bits, for outputting a row address and a first portion of a column address for each of said multiplexed memory address corresponding to the first plurality of address bits associated with the multiplexed memory address, and for outputting a second portion of the column address for each of said multiplexed memory address corresponding to the second plurality of address bits associated with the multiplexed memory address, each address buffer comprising:
• a row address buffer receiving the multiplexed memory addresses, latching in one or more bits from each of said first plurality of address bits, and outputting each corresponding row address;
• and
• a column address buffer receiving the multiplexed memory addresses, latching in one or more bits from each first plurality of address bits, outputting the corresponding first portion of each column address, latching in the second plurality of address bits, and outputting the corresponding second portion of each column address;
• row decoder circuitry coupled to the dynamic memory array and the address buffers energizing at least two word lines in the dynamic memory array in accordance with each row address:
• a column decoder coupled to the address buffers outputting a column select signal in accordance with the first and second portions of each column address;
• a sense amplifier and input/output gating circuitry coupled to the column decoder and the dynamic memory array selecting a pair of complementary digit lines of the at least two pairs of complementary digit lines in the dynamic memory array in accordance with each column select signal accessing at least two memory cells in the dynamic memory array, each memory cell coupled to one selected digit lines of the at least two pairs of complementary digit lines and one of the at least two energized word lines;
• and
• a data buffer coupled to the sense amplifier and the input/output gating circuitry communicating between accessed memory cells and external circuitry.

A memory apparatus for a semiconductor device comprising:

• a plurality of memory arrays, each memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the plurality of word lines and an access terminal coupled to one of the plurality of pairs of complementary digit lines;
• enabling circuitry for enabling effecting refreshing of the plurality of memory arrays;
• and
• word line energizing circuitry coupled to each memory array and the enabling circuitry for energizing more than one of the plurality of word lines in each memory array in accordance with each row address in response to the enabling circuitry effecting the refreshing of the at least one memory array so two or more of the plurality of memory cells are accessible through each pair of the plurality of pairs of complementary digit lines for each row address.

An integrated circuit memory device for a semiconductor device comprising:

• a plurality of memory arrays, each memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the of the plurality word lines and an access terminal coupled to one of the of the plurality of pairs of complementary digit lines;
• enabling circuitry for effecting refreshing each memory array;
• and
• word line energizing circuitry coupled to each memory array and the enabling circuitry for energizing more than one of the plurality of word lines in each memory array in accordance with each row address in response to the enabling circuitry effecting refreshing of each memory array so two or more of the plurality of memory cells are accessible through each pair of the plurality of pairs of complementary digit lines for each row address.

A wafer including a plurality of memory die, each memory die having at least one integrated circuit memory comprising:

• at least one memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the plurality of word lines and an access terminal coupled to one of the plurality of pairs of complementary digit lines;
• enabling circuitry for enabling repair of the at least one memory array;
• and
• word line energizing circuitry coupled to the at least one memory array and the enabling circuitry for energizing more than one of the plurality of word lines in the at least one memory array in accordance with each row address in response to the enabling circuitry effecting refreshing of the at least one memory array so two or more of the plurality of memory cells are accessible through each pair of the plurality of pairs of complementary digit lines for each row address.

An apparatus including an input device, an output device, a memory device, and a processor device coupled to the input, output, and the at least one memory device, the memory device comprising:

• a plurality of memory arrays, each memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the plurality of word lines and an access terminal coupled to one of the plurality of pairs of complementary digit lines;
• enabling circuitry for enabling repair of each memory array, the enabling circuitry responding to an signal to temporarily enable charging of the memory array;
• and
• word line energizing circuitry coupled to each memory array and the enabling circuitry for energizing more than one of the plurality of word lines in each memory array in accordance with each row address in response to the enabling circuitry effecting refreshing of the at least one memory array so at least two or more of the plurality of memory cells are accessible through each pair of the plurality of pairs of complementary digit lines for each row address.

A method for determining the charging of a memory array of a type to store a bit by storing a charge in a memory cell, the memory array also being of a type to access the bit by sharing the stored charge with one of two conductors and then detecting a resulting change in voltage between the one of two conductors, the method comprising:

• connecting at least two memory cells in a group of memory cells in the memory array to the one of said two conductors;
• storing the charge representing the bit in the at least two memory cells in the group of memory cells in the memory array by each memory cell of a plurality of memory cells storing the charge representing the bit;
• sharing the charge stored in each memory cell of the at least two memory cells in the group of memory cells in the memory array to share its stored charge with the one of the two conductors connected to the at least two memory cells in the group of memory cells in the memory array;
• and
• detecting the change in voltage between the one of two conductors resulting from the at least two memory cells in the group of memory cells in the dynamic memory array connected to the one of the two conductors sharing the stored charges in the at least two memory cells in the group of memory cells in the memory array with the one of the two conductors connected thereto.