Cell data protection circuit in semiconductor memory device and method of driving refresh mode

A method of driving a refresh mode in a semiconductor memory device, comprising:

• disabling a word line in a refresh mode in a same way of a normal mode;
• and
• initiating a bit line equalizing in the refresh mode slower than in the normal mode,
• wherein the bit line equalizing is initiated after the word line is completely closed so as to prevent an influence of the bit line equalizing on cell data.

A cell data protection circuit in a semiconductor memory device, comprising:

• a first delay element producing a word line disabling signal having a first delay time and a bit line sense amplifier disabling signal having the first delay time by receiving a precharge signal;
• a second delay element producing the word line disabling signal and bit line sense amplifier disabling signal having a second delay time by receiving the signals from the first delay part;
• a third delay element producing an address reset signal having a third delay time and a bit line equalizing signal having the third delay time by receiving the signals outputted from the second delay part;
• and
• a selection part outputting the signals generated from the first delay element on a refresh operation, the selection part outputting the signals generated from the second delay element in a normal operation,
• wherein the word line disabling signal and bit line equalizing signal are produced so as to satisfy a RAS precharge time (tRP) and a RAS read time (tRWL) after a write command in the normal operation and wherein the word line disabling signal and bit line equalizing signal are produced so as to leave a time interval between the word line disabling signal and bit line equalizing signal.