High-speed zero phase restart of a multiphase clock
AssigneeInfineon Technologies N.A., Inc.
InventorsMichael A. Ruegg, Sasan Cyrusian
Life of this patent
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Abstract
A high speed zero phase restart for a multiphase clock for a PRML read/write channel design. The zero phase restart includes an input for receiving a plurality of clock pulse waves, each having substantially equal period and each being out of phase with respect to other clock pulse waves; an output including at least one output terminal corresponding to one of the clock pulse waves; and a zero phase circuit configured to sequentially couple the plurality of clock pulse waves to the corresponding output terminals.
Claims12
An integrated circuit, comprising:
- an input configured for a multiphase clock signal including a plurality of clock pulse waves, each clock pulse wave being out of phase with respect to each other clock pulse wave, wherein the clock pulse waves include a most-significant-phase clock pulse wave and a least-significant-phase clock pulse wave;
- an output having a plurality of output terminals corresponding to respective ones of the plurality of clock pulse waves;
- and
- a zero phase circuit electrically coupled with the input and the output and configured to couple the plurality of clock pulse waves to the corresponding output terminals sequentially in time from the most-significant-phase clock pulse wave to the least significant phase clock pulse wave.
A method for sequentially restarting a multiphase clock signal, the method comprising the acts of:
- (a) receiving a plurality of (N) clock pulse waves, each being substantially out of phase with respect to each of the other plurality of clock pulse waves and wherein the plurality of clock pulse waves includes a most-significant-phase pulse wave and at least one least significant-phase pulse wave;
- (b) coupling the most-significant-phase pulse wave to a most significant output terminal during a first clock period;
- and
- (c) sequentially coupling after (b) the least-significant-phase clock pulse to a least significant output terminal during an Nth clock period, wherein N equals the number of clock pulse waves.
A method for synchronizing a multiphase clock signal in a PRML read/write channel, the method comprising the acts of:
- (a) receiving a plurality of (N) clock pulse waves, each being substantially out of phase with respect to each of the other plurality of clock pulse waves;
- and
- (b) sequentially coupling the plurality of clock pulse waves as a function of phase.
A computer hard disk drive, comprising:
- (a) a partial response maximum likelihood read/write channel having an oscillator circuit arranged to generate a plurality of clock signals, the clock signals being out of phase with respect to each other clock signal;
- (b) a respective plurality of logic gates coupled with the oscillator circuit and arranged to pass the clock signals to respective output terminals in response to a control signal;
- and
- (c) a plurality of respective flip/flops arranged to sequentially propagate the control signal in response to a reset signal.
Dependencies are inferred from the claim text.