Semiconductor memory device allowing easy characteristics evaluation
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakafumi Takatsuka, Masaki Tsukude
Life of this patent
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Abstract
A row control circuit includes a selector for outputting, as a signal ZRXTRSTD, either signal INTSIG or ZRXTRST in accordance with a test signal TEST, and a holding circuit for receiving a signal ZRXTS by an input A, receiving the signal ZRXTRSTD by an input B, and outputting a word line activating signal RXT from an output node OUT. In a test mode, the phase relation of a sense amplifier activating signal S0N and the word line active signal RXT is set to be different from that in a normal mode. Consequently, a margin of a timing of reading operation or restoring operation can be evaluated.
Claims7
A semiconductor memory device having a test mode and a normal mode as operation modes, comprising:
- a memory array including a plurality of memory cells arranged in a matrix;
- a plurality of word lines for selecting a row of said memory cells;
- a row decoding circuit for activating a word line corresponding to an address signal out of said plurality of word lines in accordance with a word line activating signal;
- a plurality of bit line pairs provided in correspondence with columns of said memory cells;
- a sense amplifier circuit for amplifying data held in said plurality of memory cells read on said plurality of bit line pairs in accordance with a sense amplifier activating signal;
- and
- a timing control circuit for outputting said word line activating signal and said sense amplifier activating signal in accordance with an external control signal in said normal mode, making a phase relation between said word line activating signal and said sense amplifier activating signal different from that in said normal mode and outputting the resultant phase relation in accordance with a timing test signal supplied from the outside in said test mode.
Dependencies are inferred from the claim text.