Multi-bit parallel testing for memory devices
AssigneeG-Link Technology
InventorJong-Hoon Oh
Life of this patent
Estimating the term…
Abstract
A method and apparatus for testing memory devices. One embodiment provides a method including receiving a first input data bit having a first polarity, and receiving a second input data bit having a second polarity, wherein the second polarity is the complement of the first polarity. The method also includes writing the first input data bit to a first portion of a plurality of memory cells, writing the second input data bit to a second portion of a plurality of memory cells, and reading data bits from the first and second portions of the plurality of memory cells. An active signal is generated if the data bits read from the first portion of the plurality of memory cells and complements of the data bits read from the second portion of the plurality of memory cells each have the same polarity.
Claims20
A method of testing a memory device comprising:
- receiving a first input data bit having a first polarity;
- receiving a second input data bit having a second polarity, wherein the second polarity is the complement of the first polarity;
- writing the first input data bit to a first portion of a plurality of memory cells using a first plurality of write buffers;
- writing the second input data bit to a second portion of the plurality of memory cells using a second plurality of write buffers;
- reading a first plurality of data bits from the first portion of the plurality of memory cells;
- reading a second plurality of data bits from the second portion of the plurality of memory cells;
- and
- generating an output signal if the first plurality of data bits and complements of the second plurality of data bits each have the same polarity.
A memory device comprising:
- an input/output pad;
- a first plurality of write buffers coupled to the input/output pad;
- a first plurality of multiplexers coupled to the input/output pad;
- a second plurality of write buffers, each coupled to one of the first plurality of multiplexers;
- a first plurality of memory cells, each selectively coupled to one of the first plurality of write buffers;
- a second plurality of memory cells, each selectively coupled to one of the second plurality of write buffers;
- a first plurality of sense amplifiers, each selectively coupled to one of the first plurality of memory cells;
- a second plurality of sense amplifiers, each selectively coupled to one of the second plurality of memory cells;
- and
- a second plurality of multiplexers, each coupled to one of the second plurality of sense amplifiers.
A memory device comprising:
- an input means for receiving data;
- a first writing means for receiving data from the input means and for writing data to a first plurality of memory cells;
- a first multiplexing means for receiving data from the input means and for either inverting the data or not inverting the data;
- a second writing means for receiving data from the first multiplexing means and for writing data to a second plurality of memory cells;
- a first sense amplifier means for reading data from the first plurality of memory cells;
- and
- a second sense amplifier means for reading data from the second plurality of memory cells.
A method of testing a memory device, the memory device comprising a plurality of memory cells arranged in rows and columns, wherein each memory cell is written to by one of a plurality of write circuits, the plurality of write circuits comprising a plurality of even write circuits and a plurality of odd write circuits, wherein the memory cells that are written to by an even write circuit are read by one of a plurality of even read circuits, and the memory cells that are written to by an odd write circuit are read by one of a plurality of odd read circuits, the method comprising:
- selecting a first row of memory cells;
- selecting a first column of memory cells;
- providing an input bit;
- checking if a mode bit is has a first polarity, and if it does then;
- providing the input bit to both the odd and even write circuits;
- else
- providing the input bit to the odd write circuits, and a complement of the input bit to the even write circuits;
- and
- writing from the even and odd write circuits to memory cells in the selected row and column.
Dependencies are inferred from the claim text.