US 2002/0176291 A1Published application

Method for providing a low power read only memory banking methodology with efficient bus muxing

AssigneeTexas Instruments Incorporated

InventorsHugo Cheung, Shang-Yuan Chuang

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Abstract

A low power Read Only Memory (ROM) bank accessing system with efficient bust muxing is provided. The memory access system includes separate pre-charge and pre-discharge circuits for each bit lines in the ROM bank. In a ROM bank read operation, the pre-discharge circuits and pre-charge circuits are activated and deactivated in accordance with the address of the targeted ROM bank. In an exemplary embodiment, only the pre-charge lines corresponding to the bit-line of the targeted ROM bank are pre-charged prior to the ROM read operation. Similarly, only the pre-discharge circuit corresponding to the bit lines of the targeted ROM bank is deactivated during the ROM read operation, permitting the remaining bit lines from storing residual charge.

Claims27

Dependent claims

A low power Read Only Memory bank accessing system with efficient bus muxing for use with a microcontroller, comprising:

(a) A Read Only Memory (ROM) Circuit, including at least a first ROM memory bank characterized by a first ROM memory bank address and a second ROM memory bank characterized by a second ROM memory bank address, wherein said first ROM memory bank and said second ROM memory bank further include a plurality of programmable memory cells for use in storing data said memory cell characterized by a logic level;
(b) at least a first bit line coupled to at least one of said plurality of programmable memory cells of said first ROM memory bank;
(c) at least a second bit line coupled to at least one of said plurality of programmable memory cells of said second ROM memory bank;
(d) a first pre-charge circuit coupled to said first bit line for pre-charging said at least one of said plurality of programmable memory cells of said first ROM memory bank;
(e) a second pre-charge circuit coupled to said second bit line for pre-charging said at least one of said plurality of programmable memory cells of said second ROM memory bank;
(f) a first pre-discharge circuit coupled to said first bit line for pre-discharging said at least one of said plurality of programmable memory cells of said first ROM memory bank;
(g) a second pre-discharge circuit coupled to said second bit line for pre-discharging said at least one of said plurality of programmable memory cells of said second ROM memory bank;
(h) a central processing unit for providing a desired ROM memory bank address, said desired ROM memory bank address corresponding to at least one of said first ROM memory bank and said second ROM memory bank;
(i) a ROM memory bank address decoder for decoding said desired ROM memory bank address and providing at least one of said first ROM memory bank address and said second ROM memory bank address;
and
(j) a ROM memory bank selection circuit for receiving at least one of said first ROM memory bank address and said second ROM memory bank address, said ROM memory bank selection circuit further providing a first pre-charge signal to at least one of said first pre-charge circuit and said second pre-charge circuit, said ROM memory bank selection circuit further providing a first pre-discharge signal to at least one of said first pre-discharge circuit and said second pre-discharge circuit, said first pre-charge signal and said pre-discharge signal being provided in accordance with said decoded desired ROM memory bank address.

8 more elements

A low power Read Only Memory bank accessing system with efficient bus muxing for use with a microcontroller comprising:

(a) a Read Only Memory (ROM) circuit including at least a first ROM memory bank characterized by a first ROM memory bank address and a second ROM memory bank characterized by a second ROM memory bank address, wherein said first ROM memory bank further includes a first pre-charge line, a first pre-discharge line, and a first plurality of programmable memory cells for storing a first data, said second ROM memory bank further includes a second pre-charge line, a second pre-discharge line and a second plurality of programmable memory cells for storing a second data;
(b) a first pre-charge circuit coupled to said first pre-charge line;
(c) a second pre-charge circuit coupled to said second pre-charge line;
(d) a first pre-discharge circuit coupled to said first pre-discharge line;
(e) a second pre-discharge circuit coupled to said second pre-discharge line;
and
(f) a ROM memory bank selection circuit for receiving at least one of said first ROM memory bank address and said second ROM memory bank address and providing a first pre-charge signal to at least one of said first pre-charge circuit and said second pre-charge circuit, said ROM memory bank selection circuit further providing a first pre-discharge signal at least one of said first pre-discharge circuit and said second pre-discharge circuit.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/138,386Filed 3 May 2002
Priority: 4 May 2001
Published: 28 Nov 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 17/12
In which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM: using…
G11C
Static stores