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US 2002/0176290 A1Published application
Memory architecture with refresh and sense amplifiers
AssigneeInfineon Technologies AG
InventorRaj Kumar Jain
Life of this patent
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Abstract
An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.
Claims1
A memory architecture comprising:
- an access transistor having a gate and first and second terminals;
- a storage transistor having a gate and first and second terminals, the first terminal of the storage transistor coupled to the second terminal of the access transistor;
- a refresh transistor having a gate and first and second terminals, the second terminal of the refresh transistor coupled to the second terminal of the storage transistor;
- a word line coupled to the gate of the access transistor;
- a refresh word line coupled to the gate of the refresh transistor
- a bit line coupled to the first terminal of the access transistor;
- a refresh bit line coupled to first terminals of refresh transistor;
- a sense amplifier coupled to the bit line;
- and
- a refresh amplifier coupled to the refresh bit line.
7 more elements
Dependencies are inferred from the claim text.