US 2002/0176288 A1Published application

Semiconductor integrated circuit device and test method thereof

AssigneeKabushiki Kaisha Toshiba

InventorYasuyuki Nozuyama

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.

Claims20

Dependent claims

A semiconductor integrated circuit device comprising:

a test target circuit including a plurality of nodes and terminals;
a control circuit configured to generate an internal reset signal, and an internal operation mode signal, in response to an external clock signal or an internal clock signal generated from the external clock signal, an external reset signal, and an external operation mode signal inputted therein;
and
an observation circuit configured to receive input data from observation points, which are selected from the nodes and terminals corresponding to faults not detected by a test that causes the test target circuit to perform a substantially normal functional operation, the observation circuit comprising a plurality of flip-flops,
wherein the observation circuit is controlled by the internal clock signal, the internal reset signal, and the internal operation mode signal, and is configured to reset the flip-flops in response to the internal reset signal, and to selectively perform a first operation of compressing the data from the observation points to generate a signature and a second operation of serially transferring data, using the flip-flops, in response to the internal operation mode signal, and
wherein the first operation is performed, using input data generated in the test target circuit in accordance with test patterns that cause the test target circuit to perform a substantially normal functional operation, and the second operation is performed to cause the flip-flops to be connected in series, and to read the signature out of the observation circuit.

3 more elements

A method of performing a test on a semiconductor integrated circuit device, which comprises a test target circuit including a plurality of nodes and terminals, the method comprising:

extracting from a first undetected fault list, in which faults not detected by a first fault simulation are listed, observation point candidates selected from the nodes and terminals, and observation point information including a type of each undetected fault at the observation point candidates;
sorting out the observation point candidates to obtain first observation points;
performing a second fault simulation to confirm an effect of inserting the first observation points, and obtain a second undetected fault list, by using the first observation points, circuit connection information at a first gate level, and first test patterns;
and
deleting less effective part of the first observation points, in accordance with the second fault simulation to obtain second observation points.

2 more elements

Dependencies are inferred from the claim text.