Sensing scheme of flash eeprom
AssigneeEDN Silicon Devices, Inc.
InventorYuan Tang
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Abstract
There is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations. In a second embodiment, the different reference currents are generated from a current source.
Claims20
A reading method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells, said method comprising the steps of:
- applying a fixed control gate bias voltage to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current;
- applying varied control gate bias voltages to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations;
- and
- comparing a sensed voltage corresponding to the core cell drain current and a references voltage corresponding to one of said different reference currents and generating an output signal which is at a high logic when said sensed voltage is less than said reference voltage and which is at a low logic level when said sensed voltage is higher than said reference voltage.
A reading circuit for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells, said circuit comprising:
- means for generating a fixed control gate bias voltage to be applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current;
- means for generating varied control gate bias voltages to be applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations;
- and
- means for comparing a sensed voltage corresponding to the core cell drain current and a references voltage corresponding to one of said different reference currents and for generating an output signal which is at a high logic when said sensed voltage is less than said reference voltage and which is at a low logic level when said sensed voltage is higher than said reference voltage.
A reading method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells, said method comprising the steps of:
- applying a fixed control gate bias voltage to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current;
- generating different reference currents corresponding to predetermined modes of operations from a current source;
- and
- comparing the core cell drain current and one of said different reference currents and generating an output signal which is at a high logic when the core cell drain current is higher than said one of said different reference currents and which is at a low logic level when the core cell drain current is lower than said one of said different reference currents.
Dependencies are inferred from the claim text.