US 2002/0176274 A1Published application

Ferroelectric random access memory and its operating method

AssigneeOki Electric Industry Co., Ltd.

InventorKinya Ashikaga

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Abstract

The object of the present invention is to provide a ferroelectric memory device in which an imprint is prevented, and a method of operating a ferroelectric memory device for preventing the characteristics from deteriorating due to an imprint. In a sense amp unit 113 equipped in the ferroelectric memory device, the first and the second transistors 121 and 122 connect a pair of first sub-bit lines SBL and /SBL to a ground in accordance with a sense amp control signal SAR. The third and the fourth transistors 123 and 124 connect the first sub-bit line SBL with the first sub-bit line /SBL and further connects the first sub-bit line /SBL with the second sub-bit line SSBL in accordance with the first switching control signal SASW1. The fifth and the sixth transistors 125 and 126 connect the first sub-bit line SBL with the second sub-bit line SSBL and further connects the first sub-bit line /SBL with the second sub-bit line /SSBL in accordance with the second switching control signal SASW2.

Claims8

Dependent claims

A ferroelectric memory device, in which there are included

a plurality of memory cells for storing data by polarization of a ferroelectric capacitor;
a bit line to which each of said memory cells is connected;
a pre-charge circuit, which is connected to one terminal of said bit line through a first switch unit, for providing the pre-charge voltage to said bit line;
a first sub-bit line being connected to the other terminal of said bit line through a second switch unit;
a data line for transmitting data being read out from each of said memory cells and data being written in each of said memory cells;
a second sub-bit line being connected to said data line by way of a third switch unit;
and
a sense amp unit to which said first sub-bit line and said second sub-bit line are connected, wherein said sense amp unit comprises:
a latch type sense amp for detecting a voltage of said first sub-bit line and for latching a voltage of said first sub-bit line as a predetermined level corresponding detected results;
a grounding means being capable of connecting said first sub-bit line to a ground;
a first transferring means being capable of transferring a voltage logical level of said second sub-bit line to said sub-bit line;
and
a second transferring means being capable of transferring a voltage logical level, which is reversed to the voltage logical level of said second sub-bit line, to said first sub-bit line.

10 more elements

Dependencies are inferred from the claim text.