Select line architecture for magnetic random access memories

A memory system comprising:

• a plurality of magnetic memory devices, at least one of the magnetic memory devices including:
• a plurality of global write lines for selectively conveying a destabilizing current, the global write lines being disposed from the memory cells such that the destabilizing current passing through the global write lines does not substantially disturb unselected memory cells in the memory device, each global write line including a plurality of segmented write lines operatively connected thereto;
• a plurality of segmented groups of memory cells, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line, each segmented write line being disposed in relation to the plurality of corresponding memory cells such that the destabilizing current passing through the segmented write line destabilizes the corresponding memory cells for writing;
• a plurality of segmented group select switches, each group select switch being operatively connected between a corresponding segmented write line and a global write line, the group select switch including a group select input for receiving a group select signal, the group select switch completing an electrical circuit between the corresponding segmented write line and the global write line in response to the group select signal;
• and
• a plurality of bit lines operatively coupled to each of the memory cells for selectively writing the state of the memory cells;
• and
• a decoder operatively coupled to the memory devices for selectively performing at least one of reading and writing one or more memory cells in the memory system.

A method for selectively writing one or more magnetic memory cells in a magnetic memory device, the method comprising the steps of:

• generating a destabilizing current, the destabilizing current being conveyed to selected memory cells in the memory device via a plurality of global write lines, the global write lines being disposed from the memory cells such that the destabilizing current passing through the global write lines does not substantially disturb unselected memory cells in the memory device, each global write line including a plurality of segmented write lines operatively connected thereto;
• generating a write current for writing a state of the selected memory cells, the write current being conveyed via a plurality of bit lines operatively coupled to the memory cells;
• selecting a segmented group of memory cells for writing, the segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line;
• and
• directing the write current through the bit lines, whereby each of the selected memory cells stores one of a first logic state corresponding to a first direction of the write current and a second logic state corresponding to a second direction of the write current.