Current inrush limiting circuit

#The present invention relates to circuits for limiting hot-plug or DC-side power switched inrush current and, more particularly, to an inrush limiting circuit that comprises four subsystems that cooperate with each other to effectively eliminate large inrush currents regardless of the cycle time of the device being powered or its input capacitance.

#Circuit boards, or devices containing large power supply bulk capacitance, experience an uncontrolled initial inrush current that charges the capacitance when power is initially applied. This inrush current can cause damage to components, system disruption or permanent failure thereof.

#Recent tests have shown that various point-of-sale printers have inrush current that is not properly limited. Often, attempts to resolve the problem have been primitive, and have been only marginally successful. In addition, many of these previous attempts to deal with this problem have been expensive. It is not uncommon to experience disturbances or terminal resets when POS printers are connected to a POS terminal while it is powered up.

#A complete understanding of the present invention may be obtained by reference to the accompanying drawings, when considered in conjunction with the subsequent detailed description, in which:

#FIG. 1 illustrates a block diagram of the circuit of this invention; and

#FIG. 2 depicts a more detailed diagram of the circuit of the invention.

#Generally speaking, the invention features an inrush circuit for electronic devices and, in particular, an inrush circuit for point-of-sale printers. The circuit limits hot-plug or DC-side power switched inrush current into devices having high input capacitance. The circuit applies an active feedback-controlled voltage ramp to a bulk capacitor by means of a P-channel field effect transistor that is operated linearly after a controlled delay for contact bounce. Linear output voltage ramp to the load capacitor is ensured by providing active control of the gate voltage, via an operational amplifier with voltage feedback. The ramp is generated by an RC network, but only the first third of the exponential is used, wherein the waveshape is linear and approaches that of an ideal ramp. Since a voltage ramp applied to a capacitor implies constant current, the inrush current is controlled to the extent that the ramp is linear.

#Now referring to FIG. 1, a block diagram of the inrush limiting circuit 10 of this invention is shown. The current inrush limiting circuit 10 is composed of four subsystems:

#1) A time delay 12 to eliminate false action during contact bounce.