High-speed programmable synchronous counter for use in a phase locked loop

A programmable high-speed counter, comprising:

• a clock input circuit operative to receive a clock signal at a clock input node;
• a least-significant-bit counter coupled with the clock input node and operative to decrement a least-significant-bit count value in response to the clock signal and to provide a least significant-bit zero state signal at a least-significant-bit output node;
• a most-significant-bit counter coupled with the least-significant-bit output node and operative to decrement a most-significant-bit count value in response to the least-significant-bit zero-count value and to provide a most-significant-bit zero state signal at a most-significant-bit output node;
• a count input circuit configured to receive a count value including least-significant-bits and most-significant-bits, the count input circuit operative to program the least-significant-bit counter with the least significant bits and to program the most-significant-bit counter with the most significant bits;
• and
• a counter output circuit operative to provide a clock pulse at a counter output node in response to the least-significant-bit zero state signal and the most-significant-bit zero state signal.