View DAC feedback inside analog front circuit
AssigneeInfineon Technologies N.A., Inc.
InventorSasan Cyrusian
Life of this patent
Estimating the term…
Abstract
A view DAC feedback inside an analog front circuit for a partial response, maximum likelihood based read/write channel is disclosed. The view DAC feedback circuit may be configured to apply an analog signal associated with an operation level of the PRML based read/write channel to the analog front circuit of the read channel. The view DAC analog signal may be used to calibrate operating parameters for a continuous time filter component of the analog front circuit. The view DAC feedback circuit may be configured to add digitally-controlled noise to the PRML read/write channel to optimize performance of the channel in a low signal-to-noise (SNR) environment.
Claims23
A partial response, maximum likelihood (“PRML”) read/write channel, comprising:
- an analog front circuit including electronic components configured to process analog information received from a magnetic data storage medium;
- a view digital-to-analog converter (“DAC”) circuit having a first input coupled with an internal PRML digital port having high-speed digital signals, the view DAC circuit being configured to convert the digital signals to an analog signal associated with the digital signals, the analog signal provided at a view DAC output node;
- and
- a view DAC feedback circuit coupled with the view DAC output node and being configured to selectively couple the view DAC output to the analog front circuit during a calibration procedure to optimize performance of the PRML read/write channel.
An integrated tuning circuit for a PRML read/write channel, the integrated calibration circuit comprising:
- an analog front circuit having prearranged electronic components configured to process analog information received from a magnetic data storage medium, the electronics components including an impedance and squelch control component, a variable gain amplifier component, a magnetic read asymmetry component;
- an offset correction component and a continuous time filter component;
- a view DAC circuit operative to receive a 7-bit digital data from an to internal digital bus of the PRML read/write channel and a clock signal from a synthesizer circuit, the view DAC being operative to convert the 7-bit digital data and the clock signal to an analog signal provided at a view DAC output, the analog signal associated with a performance level for the PRML read/write channel;
- a first view DAC feed back circuit having a first input coupled with the view DAC output, a second input coupled with the impedance and squelch control circuit and an output coupled with the variable gain amplifier component, the first view DAC feedback operative to selectively couple the impedance and squelch control component and the view DAC output to the variable gain amplifier;
- and
- a second view DAC feedback circuit having an input coupled with the view DAC output and an output coupled with a summing node, the second view DAC feedback circuit being operative to selectively couple the view DAC circuit with the summing node, the summing node being coupled with an output of the magnetic read asymmetry component and with an output of the offset correction component and providing an input to the continuous time filter component.
A method of tuning a PRML based read/write channel, the method comprising the acts of:
- generating an analog signal associated with a performance level of the PRML based read channel, the analog signal being generated from digital information from an internal digital bus;
- and
- selectively coupling the analog signal to an analog front circuit for a read component of the PRML read/write channel.
A hard disk drive, comprising:
- a magnetic storage medium having at least one platter configured to store data as magnetic flux;
- a head operative to read data from and write data to the magnetic storage medium, the head providing an analog data signal at a head output;
- a PRML based read/write channel coupled with the head output and operative to receive and process the analog data signal provided by the head, the PRML based read/write channel having a read circuit with an analog front circuit;
- a view DAC circuit coupled with the PRML based read/write channel and operative to generate an analog signal from a digital clock signal and internal digital signals at an internal 7-bit digital port of the PRML read/write channel, the analog signal associated with a performance level for the PRML based read/write channel and being provided at a view DAC output;
- and
- a view DAC feedback circuit coupled with the view DAC output and being operative to selectively couple the view DAC output with the analog front circuit.
Dependencies are inferred from the claim text.