US 2002/0176118 A1Published application

Apparatus and method for consolidating output data from a plurality of processors

AssigneeQUALCOMM Incorporated

InventorsJudith LaRocca, Ann Chris Irvine

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Abstract

In a system having a plurality of processors 1 to M and each processor has corresponding output registers 1 to N an apparatus and method to transfer is claimed. The data comprises a current group of data and a next group of data. Each group of data comprises a plurality of portions of data. The current group of data from each processor 1 to M is transferred to its corresponding output register 1 to N. Each processor then receives and processes the next group of data. Simultaneously, the portion of data from output register N to output register N-1 is transferred. Similarly, each portion of data from output register N-1 is transferred to output register N-2, and so on. The portion of data from register 1 is transferred to a frame buffer.

Claims30

Dependent claims

An apparatus to consolidate the output of data, the data comprising a plurality of data elements, the apparatus comprising:

a plurality of processors, each processor comprising:
an input register configured to receive a predetermined quantity of data elements;
at least one butterfly processor coupled to the input register, the butterfly processor configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements;
at least one intermediate register coupled to the butterfly processor, the intermediate register configured to temporarily store the processed data;
and
a feedback loop coupling the intermediate register and the butterfly processor, where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and, where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register;
wherein the holding register is configured to store the processed data until all of the first portion data elements is processed;
and
a plurality of output registers associated with the plurality of processors, wherein each output register is coupled to the holding register and another output register, each output register configured to receive the processed data from the holding register and route the processed data to an output register of a different processor.

6 more elements

In a system having a plurality of processors 1 to M, each processor having a corresponding output register 1 to N configurable to receive and transfer data, a method to determine an inverse transform of a block of encoded data, the block of encoded data comprising a current group of data and a next group of data, each group comprising a plurality of data elements, the method comprising:

(a) receiving a predetermined quantity of data elements;
(b) performing at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements;
(c) making a determination as to whether any of the processed data elements require additional mathematical operations;
(d) selecting a first portion of processed data elements that require additional mathematical operations;
(e) selecting a second portion of processed data elements that do not require additional mathematical operations;
(f) performing at least one mathematical operation on selected pairs of the first portion of processed data elements to produce a second output of processed data elements;
and
(g) storing the second portion of processed data elements until all of the first portion of data elements is processed;
(h) repeating steps (c), (d), (e), (f) and (g) as necessary until all portions of the data are processed;
(i) transferring the current group of data from each processor 1 to M its corresponding output register 1 to N;
(j) receiving and processing the next group of data within each processor;
and simultaneously to (i) and (j),
(k) transferring the portion of data from output register N to output register N-1, the portion of data from output register N-1 to output register N-2, and so on;
and
(l) transferring the portion of data from register 1 to a frame buffer.

12 more elements

In a system having a plurality of processors 1 to M, each processor having a corresponding output register 1 to N configurable to receive and transfer data, an apparatus to determine an inverse transform of a block of encoded data, the block of encoded data comprising a first group of data and a next group of data, each group comprising a plurality of data elements, the apparatus comprising:

(a) means for receiving a predetermined quantity of data elements;
(b) means for performing at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements;
(c) means for making a determination as to whether any of the processed data elements require additional mathematical operations;
(d) means for selecting a first portion of processed data elements that require additional mathematical operations;
(e) means for selecting a second portion of processed data elements that do not require additional mathematical operations;
(f) means for performing at least one mathematical operation on selected pairs of the first portion of processed data elements to produce a second output of processed data elements;
and
(g) means for storing the second portion of processed data elements until all of the first portion of data elements is processed;
(h) means for repeating steps (c), (d), (e), (f) and (g) all portions of the data are processed;
(i) means for transferring the current group of data from each processor 1 to M its corresponding output register 1 to N;
(j) means for receiving and processing the next group of data within each processor;
and simultaneous to (i) and (j),
(k) means for transferring the portion of data from output register N to output register N-1, the portion of data from output register N-1 to output register N-2, and so on;
and
(l) means for transferring the portion of data from register 1 to a frame buffer.

12 more elements

Dependencies are inferred from the claim text.