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US 2002/0175919 A1Published application
Graphic accelerator
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHiroshi Kuranaga
Life of this patent
Estimating the term…
Abstract
In the graphic accelerator, control section reads pixel data of 1 word among pixel data in the S and D areas and makes the S and D buffers respectively store the resulting data. Furthermore, the data pass section transfers the pixel data of the S buffer to the first WRT buffer, transfers the pixel data of the D buffer to the second WRT buffer. The pixel data in the second WRT buffer is written in the corresponding S area, and the pixel data in the first WRT buffer is written in the corresponding D area.
Claims6
A graphic accelerator comprising:
- a memory having a source area and a destination area;
- a first buffer which holds pixel data read from said source area of said memory;
- a second buffer which holds pixel data read from said destination area of said memory;
- a third buffer which holds pixel data to be written into said memory;
- a fourth buffer which holds pixel data to be written into said memory;
- a reading unit which reads pixel data from said source area of said memory and makes said first buffer store the read pixel data, reads pixel data from said destination area of said memory makes said and makes second buffer store the read pixel data, in a unit of access to said memory;
- a transfer unit which makes said first buffer to transfer the pixel data held in said first buffer to said third buffer, and makes said second buffer to transfer the pixel data held in said second buffer to said fourth buffer;
- and
- a writing unit which writes the pixel data held in said fourth buffer in said source area of said memory and writes the pixel data held in said third buffer in said destination area of said memory.
6 more elements
Dependencies are inferred from the claim text.