Multi-bit delta sigma A/D converter

A multi-bit ΔΣ A/D converter comprising “k” constitution stages (where “k” is a positive integer) connected in cascade, each of said constitution stages including an analog adding means receiving an analog input signal and an analog feedback signal for outputting a difference between said analog input signal and said analog feedback signal, an analog integrating means for integrating an output signal of said analog adding means, and an analog multiplying means for multiplying an output of said analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of said analog multiplying means of the “k”th stage with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from said multi-bit quantizing means into an analog signal, said D/A converting means outputting said analog signal to said analog adding means of said “k” stages, as said analog feedback signal in a next sampling time, wherein there is provided a digital processing means receiving said digital output signal outputted from said multi-bit quantizing means, for outputting a sum of said digital output signal and a value obtained by multiplying said digital output signal outputted before a predetermined time, by a predetermined coefficient, said digital processing means successively performing a similar adding processing for a result of said summing (k−1) times, and a value obtained by subtracting from an output of said digital processing means a value obtained by differentiating a predetermined quantization noise, is outputted.

A multi-bit ΔΣ A/D converter comprising an analog adding means for outputting a difference between an analog input signal and an analog feedback signal, an analog integrating means for integrating an output signal of said analog adding means, an analog multiplying means for multiplying an output of said analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of said analog multiplying means with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from said multi-bit quantizing means into an analog signal, said D/A converting means outputting said analog signal as said analog feedback signal in a next sampling time,

• wherein said multi-bit quantizing means includes a n-bit quantizer (where “n” is an integer not less than 2) and a most significant bit extractor located at a stage following said n-bit quantizer.
• wherein there is provided a digital processing means including a first delay means receiving an output of said n-bit quantizer, for holding said output of said n-bit quantizer for a predetermined time, a first digital multiplying means for multiplying an output of said first delay means by a predetermined coefficient, a first digital adding means for outputting a sum of the output of said n-bit quantizer and an output of said first digital multiplying means, a second delay means receiving a quantization noise mixed into with said most significant bit extractor, for holding said quantization noise for a predetermined time, a second digital multiplying means for multiplying an output of said second delay means by a predetermined coefficient, and a second digital adding means for outputting a sum of the output of said first digital adding means and an output of said second digital multiplying means, as an output of the multi-bit ΔΣ A/D converter.

A multi-bit ΔΣ A/D converter comprising two constitution stages connected in cascade, each of said constitution stages including an analog adding means for outputting a difference between an analog input signal and an analog feedback signal, an analog integrating means for integrating an output signal of said analog adding means, and an analog multiplying means for multiplying an output of said analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of said analog multiplying means of the second stage with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from said multi-bit quantizing means into an analog signal, said D/A converting means outputting said analog signal to said analog adding means of each stages, as said analog feedback signal in a next sampling time,

• wherein said multi-bit quantizing means includes a n-bit quantizer (where “n” is an integer not less than 2) and a most significant bit extractor located at a stage following said n-bit quantizer.
• wherein there is provided a digital processing means including a first delay means receiving an output of said n-bit quantizer, for holding said output of said n-bit quantizer for a predetermined time, a first digital multiplying means for multiplying an output of said first delay means by a predetermined coefficient, a first digital adding means for outputting a sum of the output of said n-bit quantizer and an output of said first digital multiplying means, a second delay means for holding the output of said first delay means for a predetermined time, a second digital multiplying means for multiplying an output of said second delay means by a predetermined coefficient, a second digital adding means for outputting a sum of the output of said first digital adding means and an output of said second digital multiplying means, a third digital multiplying means receiving a quantization noise mixed into with said most significant bit extractor, for multiplying said quantization noise by a predetermined coefficient, a third delay means for holding an output of said third digital multiplying means for a predetermined time, a third digital adding means for outputting a sum of the output of the second digital adding means and an output of said third delay means, a fourth digital multiplying means for multiplying an output of said third delay means by a predetermined coefficient, a fourth digital adding means for outputting a sum of said third digital adding means and an output of said fourth digital multiplying means, a fourth delay means for holding an output of said third delay means for a predetermined time, and a fifth digital adding means for outputting a sum of the output of said fourth digital adding means and an output of said fourth delay means, as an output of the multi-bit ΔΣ A/D converter.

A multi-bit ΔΣ A/D converter comprising three constitution stages connected in cascade, each of said constitution stages including an analog adding means for outputting a difference between an analog input signal and an analog feedback signal, an analog integrating means for integrating an output signal of said analog adding means, and an analog multiplying means for multiplying an output of said analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of said analog multiplying means of the final stage with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from said multi-bit quantizing means into an analog signal, said D/A converting means outputting said analog signal to said analog adding means of each stages, as said analog feedback signal in a next sampling time,

• wherein said multi-bit quantizing means includes a n-bit quantizer (where “n” is an integer not less than 2) and a most significant bit extractor located at a stage following said n-bit quantizer.
• wherein there is provided a digital processing means including a first delay means receiving an output of said n-bit quantizer, for holding said output of said n-bit quantizer for a predetermined time, a first digital multiplying means for multiplying an output of said first delay means by a predetermined coefficient, a first digital adding means for outputting a sum of the output of said n-bit quantizer and an output of said first digital multiplying means, a second delay means for holding the output of said first delay means for a predetermined time, a second digital multiplying means for multiplying an output of said second delay means by a predetermined coefficient, a second digital adding means for outputting a sum of the output of said first digital adding means and an output of said second digital multiplying means, a third delay means for holding the output of said second delay means for a predetermined time, a third digital multiplying means for multiplying an output of said third delay means by a predetermined coefficient, a third digital adding means for outputting a sum of the output of said second digital adding means and an output of said third digital multiplying means, a fourth digital multiplying means receiving a quantization noise mixed into with said most significant bit extractor, for multiplying said quantization noise by a predetermined coefficient, a fourth delay means for holding an output of said fourth digital multiplying means for a predetermined time, a fifth digital adding means for multiplying an output of said fourth delay means by a predetermined coefficient, a fourth digital adding means for outputting a sum of the output of the third digital adding means and an output of said fifth digital adding means, a fifth delay means for holding an output of said fourth delay means for a predetermined time, a sixth digital multiplying means for multiplying an output of said fifth delay means by a predetermined coefficient, a fifth digital adding means for outputting a sum of said fourth digital adding means and an output of said fifth digital multiplying means, a sixth delay means for holding an output of said fifth delay means for a predetermined time, and a sixth digital adding means for outputting a sum of the output of said fifth digital adding means and an output of said sixth delay means, as an output of the multi-bit ΔΣ A/D converter.