Method and apparatus for a signal processing circuit
OwnerThomas Freyinventor
Life of this patent
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Abstract
A method and apparatus for digital signal processing is described. The present method and apparatus for digital signal processing processes data using an inventive pipelined architecture including multiple processing stages. A processing stage causes the next processing stage in the pipeline to become active by selectively enabling a clock signal to the next processing stage without requiring a central controller. Thus, each stage flexibly and dynamically self adjusts its effective clock frequency to a level that is appropriate and respective to current demanded data throughput and data processing requirements.
Claims34
A signal processing (SP) circuit, comprising:
- (a) a plurality of processing stages, comprising a first processing stage and a last processing stage, wherein at least one of each said processing stages is configured to receive an associated and respective data signal and control signal, and wherein the first processing stage receives an input data signal and an input control signal, and wherein subsequent processing stages receive a previous stage data signal and a corresponding previous stage control signal from a previous stage;
- and
- (b) a plurality of clock signal controllers comprising a first clock signal controller and a last clock signal controller, wherein at least one of each said clock signal controllers is operatively connected to an associated and respective processing stage, and wherein at least one of each said clock signal controllers is configured to receive a control signal associated with and corresponding to its associated and respective processing stage and a common reference clock signal, and wherein the at least one of each said clock signal controllers inputs a processing stage clock signal to its associated processing stage responsive to the associated and respective control signal.
A method of processing data signals in a signal processing (SP) circuit, wherein the SP circuit comprises a plurality of processing stages having a plurality of clock signal controllers, wherein the plurality of processing stages comprises a first processing stage and a last processing stage, and wherein the plurality of clock signal controllers comprises a first clock signal controller and a last clock signal controller, and wherein at least one of each said clock signal controllers is operatively connected to an associated and respective processing stage, the method comprising the acts of:
- (a) receiving an input data signal and an input control signal;
- (b) monitoring the input control signal and proceeding to act (c) only when the input control signal is enabled;
- (c) generating a processing stage clock signal from a common reference clock signal;
- (d) processing the input data signal using the processing stage clock signal generated in act (c);
- (e) transmitting the input data signal processed in act (d) to a next processing stage and providing a next processing stage input control signal to a next clock signal controller;
- and
- (f) repeating acts (a)-(e) for processing stage until the last processing stage is enabled.
An apparatus for processing data signals in a signal processing (SP) circuit, the apparatus comprising:
- (a) means for receiving an input data signal and an input control signal;
- (b) means, operatively connected to the receiving means, for generating a processing stage clock signal from a common reference clock signal when the input control signal is enabled;
- (c) means, operatively connected to the clock signal generating means, for processing the input data signal using the processing stage clock signal;
- (d) means, operatively connected to the processing means, for transmitting the processed input data signal to a next processing stage and providing a next stage input control signal to a next clock signal generating means;
- (e) means, operatively connected to the processing means, for outputting the input data signal and the input control signal;
- and
- (f) means, operatively connected to a last processing stage, for transmitting a sleep control signal to a last clock signal generating means.
A computer program executable on a general purpose computing device, wherein the program is capable of processing data signals in a signal processing (SP) circuit, the computer program comprising:
- (a) a first set of instructions for receiving an input data signal and an input control signal;
- (b) a second set of instructions for generating a processing stage clock signal from a common reference clock signal when the input control signal is enabled;
- (c) a third set of instructions for processing the input data signal using the processing stage clock signal;
- (d) a fourth set of instructions for transmitting the processed input data signal to a next processing stage and for providing a next input control signal to a next clock signal controller;
- (e) a fifth set of instructions for outputting the processed input data signal and a valid data control signal;
- and
- (f) a sixth set of instructions for transmitting a sleep control signal to a last clock signal controller.
Dependencies are inferred from the claim text.