System and method for rate adaptation in a wireless communication system

A telecommunication device, comprising:

• a GSM baseband master processor;
• a TDMA baseband co-processor situated uplink from said GSM baseband master processor;
• an uplink buffer pair, including a transmit exchange buffer;
• a downlink buffer pair including a receive exchange buffer;
• a counter for counting movement of an exchange buffer pointer;
• a filter coupled to receive an output of said counter;
• and
• an exchange buffer adjustment unit for adjusting a size of an exchange buffer responsive to an output of said filter.

A telecommunications method, comprising:

• counting a number of bits between consecutive frames;
• filtering a count to minimize jitter;
• and
• adjusting an exchange buffer size if said count is other than a predetermined count.

A method, comprising:

• providing first circuitry in a first clock domain operable at a first clock frequency;
• providing second circuitry in a second clock domain operable at a second clock frequency;
• providing first and second jitter buffers interfacing between said first circuitry and said second circuitry domain;
• wherein said first or second jitter buffers alternately fill at said first clock frequency and empty at said second clock frequency, wherein alternation between said first and second jitter buffers occurs at said second clocking frequency.

A system, comprising:

• first circuitry in a first clock domain operable at a first clock frequency;
• second circuitry in a second clock domain operable at a second clock frequency;
• first and second pairs of jitter buffers interfacing between said first circuitry and said second circuitry domain;
• wherein ones of said pairs of first or second jitter buffers are swapped according to a clock by which said ones of said pairs of first or second jitter buffers are filled or emptied.

A system, comprising:

• first circuitry in a first clock domain operable at a first clock frequency;
• second circuitry in a second clock domain operable at a second clock frequency;
• first and second jitter buffer pairs interfacing between said first circuitry and said second circuitry domain, said first jitter buffer pair comprising first and second jitter buffers, and said second jitter buffer pair comprising third and fourth jitter buffers;
• wherein said first or second jitter buffers and said third or fourth jitter buffers alternately fill at said first clock frequency and empty at said second clock frequency, wherein alternation between said first and second jitter buffers and said third and fourth jitter buffers occurs at said second clocking frequency.

A telecommunication system, comprising:

• an audio input;
• an audio output;
• interface circuitry comprising first and second jitter buffers operably coupling said audio input to a voice encoder and third and fourth jitter buffers operably coupling said audio output to a voice decoder;
• wherein said first or second jitter buffers alternately fill at a first clock frequency and empty at a second clock frequency, wherein alternation between said first and second jitter buffers occurs at said second clock frequency;
• and
• wherein said third or fourth jitter buffers alternately fill at said second clock frequency and empty at said first clock frequency, wherein alternation between said third and fourth jitter buffers occurs at said second clock frequency.