Device isolation process flow for ARS system
AssigneeHewlett-Packard Develpoment Company, L.P.
InventorsHeon Lee, Chung-Ching Yang, Peter Hartwell
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Abstract
A device isolation process flow for an atomic resolution storage (ARS) system inserts device isolation into a process flow of the ARS system so that diodes may be electrically insulated from one another to improve signal to noise ratio. In addition, since most harsh processing is done prior to depositing a phase change layer, which stores data bits, process damage to the phase change layer may be minimized.
Claims20
A method for device isolation for an atomic resolution storage (ARS) system, comprising:
- forming an insulating layer between a wafer substrate and a top active silicon (Si) layer;
- forming a phase change layer over the top active Si layer;
- depositing a masking layer over the phase change layer, wherein the masking layer is patterned and selectively etched;
- and
- etching the top active Si layer using the masking layer as a mask until reaching the insulating layer, whereby devices embedded in the top active Si layer become electrically isolated from one another.
An apparatus with isolated devices for an atomic resolution storage (ARS) system, comprising:
- a first wafer, wherein the first wafer includes field emitters that create electron beams by drawing electrons off a metal in the field emitters, and wherein the electron beams are used to write data bits onto storage media;
- and
- a second wafer, wherein the second wafer is a highly doped silicon (Si) substrate, the second wafer comprises:
- devices embedded in atop active Si layer, wherein the devices are isolated from one another, and each device is coupled with each field emitter in the second wafer;
- and
- an insulating layer positioned between the second wafer substrate and the top active Si layer, wherein the devices are isolated by etching of the top active Si layer until reaching the insulating layer in the second wafer.
A method for device isolation for an atomic resolution storage (ARS) system, comprising:
- forming an insulating layer between a wafer substrate and a top active silicon (Si) layer;
- forming a phase change layer over the top active Si layer;
- depositing a masking layer over the phase change layer;
- patterning the masking layer;
- selectively etching the masking layer;
- and
- etching the top active Si layer using the masking layer as a mask until reaching the insulating layer, whereby devices embedded in the top active Si layer become electrically isolated from one another.
Dependencies are inferred from the claim text.