Method for fabricating contact holes in DRAM circuits

Abstract

The present invention provides a method for fabricating contact holes in DRAM circuits, comprising the steps of: providing a semiconductor substrate and forming a gate dielectric layer, a gate material layer and a first dielectric layer; patterning the gate dielectric layer, the gate material layer and the first dielectric layer, so as to form a gate structure on an active region and an interconnection structure on a field oxide region; depositing a second dielectric layer and etching the second dielectric layer so as to form spacers on the gate structure and the interconnection structure; forming source/drain regions on the semiconductor substrate; depositing and patterning a first photoresist layer so as to expose the surface of the first dielectric layer of the interconnection structure; etching the first dielectric layer of the interconnection structure until the gate material layer of the interconnection structure is exposed; removing the first photoresist pattern; depositing a third dielectric layer composed of a different material from the first and the second dielectric layers; depositing and patterning a second photoresist layer on the third dielectric layer; etching the third dielectric layer, so as to form a first contact hole opening and a second contact hole opening, wherein the first contact hole opening exposes the source/drain region on the active region and the second contact hole opening exposes the gate material layer on the interconnection structure; and filling the contact hole openings with a conductor material. In this manner, self-aligned contact holes are completed.

Dependencies are inferred from the claim text.