US 2002/0173139 A1 · Fabricating ferroelectric memory device

Abstract

Methods for fabricating a ferroelectric memory device are disclosed, in which the cracking of the ferroelectric thin film can be inhibited during a heat treatment in a scribe lane region (for forming an aligning key and an overlay vernier). A first interlayer dielectric film is formed upon a semiconductor substrate on which the transistor has been formed. The first interlayer dielectric film is selectively etched to form a first contact hole and to expose a source/drain. A first conductive film is formed on an entire surface that includes the first contact hole. The first conductive film is selectively etched to form a first conductive pad, the first conductive pad being connected through the first contact hole to the source/drain. A second interlayer dielectric film is formed on an entire surface that includes the first conductive film. The second interlayer dielectric film is selectively etched to form a second contact hole and to expose the first conductive pad so as to form an aligning key region in the scribe lane region. A second conductive film is formed on an entire surface that includes the second contact hole. The second conductive film is selectively etched to form a plug, the plug being connected through the second contact hole to the first conductive pad.

Claims19

Dependent claims

A method for fabricating a ferroelectric memory device, comprising:

forming a transistor on a cell region of a semiconductor substrate, the semiconductor substrate including the cell region and a scribe lane region, and the transistor including a source/drain;
forming a first interlayer dielectric film upon the transistor;
selectively etching the first interlayer dielectric film to form a first contact hole and to expose the source/drain;
forming a first conductive film on an entire surface (including the first contact hole);
selectively etching the first conductive film to form a first conductive pad, the first conductive pad being connected through the first contact hole to the source/drain;
forming a second interlayer dielectric film on an entire surface (including the first conductive film);
selectively etching the second interlayer dielectric film to form a second contact hole and to expose the first conductive pad so as to form an aligning key region in the scribe lane region;
forming a second conductive film on an entire surface (including the second contact hole);
selectively etching the second conductive film to form a plug, the plug being connected through the second contact hole to the first conductive pad;
and
sequentially forming a lower electrode, a ferroelectric thin film and an upper electrode on the second interlayer dielectric film (including the plug).

8 more elements

A method for fabricating a ferroelectric memory device, comprising the steps of:

forming a transistor on a cell region of a semiconductor substrate, the semiconductor substrate including the cell region and a scribe lane region, and the transistor including a source/drain;
forming a first interlayer dielectric film on an entire surface (including the transistor);
selectively etching the first interlayer dielectric film to form a first contact hole and to expose a dopant junction layer;
simultaneously forming a bit line and a landing pad so as to be connected through the first contact hole to the dopant junction layer;
forming a second interlayer dielectric film on an entire surface (including the bit line and the landing pad);
selectively etching the second interlayer dielectric film to form a second contact hole and to expose the landing pad so as to form an aligning key region in the scribe lane region;
burying a stacked film of a plug and a barrier film into the second contact hole;
and
sequentially forming a lower electrode, a ferroelectric thin film and an upper electrode on an entire surface (including the barrier film).

6 more elements

Dependencies are inferred from the claim text.

Fabricating ferroelectric memory device

Life of this patent

Fabricating ferroelectric memory device

Life of this patent

Abstract

Claims19