Combined barrier layer and seed layer
AssigneeMicron Technology, Inc.
InventorDinesh Chopra
Life of this patent
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Abstract
Methods and apparatus for forming conductive interconnect layers useful in articles such as semiconductor chips, memory devices, semiconductor dies, circuit modules, and electronic systems. The number of necessary processing steps to form conductive interconnects are reduced by removing the need to employ a seed layer interposed between the barrier layer and the conductive interconnect layer. This is accomplished in part through the electrochemical reduction of oxides on a dual-purpose layer. The present invention can be advantageously utilized to deposit copper interconnects onto tungsten.
Claims94
A method of metallizing a substrate, comprising:
- depositing a dual-purpose layer on the substrate;
- electrochemically reducing oxides on the surface of the dual-purpose layer;
- and
- electrochemically depositing a conductive interconnect layer on the surface of the dual-purpose layer.
A method of metallizing a substrate, comprising:
- depositing a dual-purpose layer on the substrate;
- electrochemically reducing oxides on the surface of the dual-purpose layer in an electrochemical reaction cell comprising an anode formed from a material that can be oxidized in the presence of the material comprising the dual-purpose layer;
- and
- electrochemically depositing a conductive interconnect layer on the surface of the dual-purpose layer.
A method of metallizing a substrate, comprising:
- depositing a dual-purpose layer on the substrate;
- electrochemically reducing oxides on the surface of the dual-purpose layer utilizing a first electrolyte;
- and
- electrochemically depositing a conductive interconnect layer on the surface of the dual-purpose layer utilizing a second electrolyte.
A method of metallizing a substrate, comprising:
- depositing a dual-purpose layer on the substrate;
- electrochemically reducing oxides on the surface of the dual-purpose layer;
- and
- electrochemically depositing a conductive interconnect layer on the surface of the dual-purpose layer, wherein both the electro chemically reducing step and the
- electrochemically depositing step are performed in a single electrochemical reaction cell utilizing a single electrolyte.
An electrochemical reaction cell comprising:
- an electrical power source;
- a cathode electrically connected to the electrical power source;
- an anode electrically connected to the electrical power source and the cathode;
- and
- an electrolyte comprising:
- a metal cation;
- a counterion;
- a complexing agent;
- and
- a pH control agent.
A semiconductor, comprising:
- a conductive interconnect layer electrochemically deposited onto a dual-purpose layer.
A memory device, comprising:
- an address decoder;
- row access circuitry;
- column access circuitry;
- control circuitry;
- an input output circuit;
- and
- an array of memory cells, wherein at least one of the memory cells comprises a conductive interconnect layer electrochemically deposited onto a dual-purpose layer.
A semiconductor die produced from a semiconductor wafer, comprising:
- an individual pattern on a substrate that contains circuitry or integrated circuit devices, wherein the circuitry or integrated circuit device performs a specific function, and wherein at least one of the integrated circuit devices comprises a conductive interconnect layer electrochemically deposited onto a dual-purpose layer.
A circuit module, comprising a combination of two or more semiconductor dies, to form a circuit module for enhancing or extending the functionality of an individual semiconductor die, wherein one or more of the semiconductor dies comprises a conductive interconnect layer electrochemically deposited onto a dual-purpose layer.
An electronic system, comprising:
- one or more circuit modules and a user interface, wherein at least one of the circuit modules comprises a conductive interconnect layer electrochemically deposited onto a dual-purpose layer.
Dependencies are inferred from the claim text.