Integration of High K Gate Dielectric
AssigneeASM America, Inc.
InventorsChristophe F. Pomerede, Michael E. Givens, Eric J. Shero, Michael A. Todd
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AssigneeASM America, Inc.
InventorsChristophe F. Pomerede, Michael E. Givens, Eric J. Shero, Michael A. Todd
Estimating the term…
Abstract of Disclosure Methods are provided herein for forming electrode layers over high dielectric constant (high k) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes aid in reducing hydrogen content for a given deposition rate.
A method of forming a transistor gate stack, comprising:
The method of Claim 15, wherein the carrier gas comprises nitrogen.
A method of forming a structure in an integrated circuit, comprising:
A method of forming a silicon-containing material over a high dielectric constant material, comprising:
The method of Claim 37, wherein the silicon source gas comprises silane.
Dependencies are inferred from the claim text.