Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices

Abstract

A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-overlapping relationship with the gate layer. This device outperforms conventional devices in terms of performance. Lower external resistance is achieved by forming a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, forming portions of the gate underneath the spacers, electrical gate control of the shallow LDD junctions is made possible. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance. A method for making the gate-controlled device includes forming the source/drain regions and shallow LDD extensions before deposition of the gate. This advantageously allows high-k dielectrics to be used in the device with reduced temperature stability. Further, the method may be performed in a self-aligned manner, which allows for dopant dose reduction with a commensurate reduction in junction capacitance.

Dependencies are inferred from the claim text.