Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same

A semiconductor memory device having a memory cell array region, a peripheral circuit region and a connection region between said memory cell array region and said peripheral circuit region, comprising:

• ferroelectric capacitors formed on a semiconductor substrate via an interlayer insulating film in said memory cell array region;
• and
• conductive films formed on said interlayer insulating film in said connection region, and
• wherein said conductive films are connected with said semiconductor substrate via conductive routes passing through said interlayer insulating film, respectively.

A method of manufacturing a semiconductor memory device, comprising the steps of:

• (a) forming MOS transistors in a memory cell array region and a connection region outside said memory cell array region, wherein a density of said MOS transistors in said memory cell array region is substantially the same as that of said MOS transistors in said connection region;
• (b) forming an interlayer insulating film to cover said MOS transistors while forming thermally conductive routes, each of which extends from one of said MOS transistors to pass through said interlayer insulating film;
• (c) forming a lower electrode film on a semiconductor substrate via said interlayer insulating film to be connected with said thermally conductive routes;
• (d) forming a ferroelectric film on said lower electrode layer while heating said lower electrode layer;
• (e) forming an upper electrode film on said ferroelectric film;
• and
• (f) forming ferroelectric capacitors in said memory cell array region, each of said ferroelectric capacitors comprising said lower electrode film, said ferroelectric film and said upper electrode film.

A method of manufacturing a semiconductor memory device, comprising the steps of:

• (a) forming MOS transistors in a memory cell array region and a connection region outside said memory cell array region, wherein a density of said MOS transistors in said memory cell array region is substantially the same as that of said MOS transistors in said connection region;
• (b) forming an interlayer insulating film to cover said MOS transistors while forming thermally conductive routes, each of which extends from one of said MOS transistors to pass through said interlayer insulating film;
• (c) forming a lower electrode film on a semiconductor substrate via said interlayer insulating film to be connected with said thermally conductive routes;
• (d) forming a ferroelectric film on said lower electrode layer while heating said lower electrode layer via said thermally conductive routes on a side of said semiconductor substrate;
• (e) forming an upper electrode film on said ferroelectric film;
• and
• (f) forming ferroelectric capacitors in said memory cell array region, each of said ferroelectric capacitors comprising said lower electrode film, said ferroelectric film and said upper electrode film.