US 2002/0173108 A1Published application

Method of forming a LD MOS

OwnerChing-Chun Huang, Sheng-Hsiung Yanginventors

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Abstract

A P-well and an N-well adjacent to the P-well are formed within a semiconductor substrate. A silicon nitride layer having an opening and a silicon oxide layer are then formed, respectively, on the semiconductor substrate. The silicon oxide layer fills the opening in the silicon nitride layer. Following that, a chemical mechanical polishing process removes portions of the silicon oxide layer to align the surface of the remaining silicon oxide layer with the surface of the silicon nitride layer to form an insulator. Subsequently, the silicon nitride layer is completely removed followed by forming a gate layer positioned on the P-well and N-well, a side of the gate layer being positioned on the surface of the insulator. Finally, an ion implantation process is performed to form N-type doping regions on the P-well and the N-well as a source and a drain of an LD MOS transistor, completing fabrication of the LD MOS transistor.

Claims18

Dependent claims

A method of forming a lateral diffused metal-oxide semiconductor (LD MOS) transistor on a semiconductor wafer, the surface of the semiconductor wafer comprising a silicon substrate, a p-well and a n-well both positioned in the silicon substrate and the p-well being adjacent to the n-well, the method comprising:

forming a silicon nitride layer on the silicon substrate;
performing a lithographic process to form a photo-resist layer on the silicon nitride layer, the photo-resist layer being used to define a position of an insulator;
using the photo-resist layer as a mask to perform an etching process to form an opening in the silicon nitride layer;
stripping the photo-resist layer;
performing a deposition process to form a silicon oxide layer on the silicon nitride layer, and filling the opening in the silicon nitride layer;
performing a chemical mechanical polishing (CMP) process to remove portions of the silicon oxide layer to align the surface of the silicon oxide layer with the surface of the silicon nitride layer, wherein the silicon oxide layer remaining in the opening in the silicon nitride layer forms the insulator;
removing the silicon nitride layer;
forming a gate layer positioned on a portion of the surfaces of both the p-well and n-well, and a side of the gate layer positioned on the surface of the insulator;
and
performing an ion implantation process to form a doped region positioned on the p-well and a doped region positioned on the n-well, the two doped regions functioning as source and drain of the LD MOS transistor.

7 more elements

forming both a p-well and a n-well in the silicon substrate, and the p-well being adjacent to the n-well;
forming a first silicon nitride layer on the silicon substrate, the silicon nitride layer comprising an opening within it;
performing a deposition process to form a silicon oxide layer on the first silicon nitride layer, and filling the opening in the first silicon nitride layer;
performing a chemical mechanical polishing (CMP) process to remove portions of the silicon oxide layer to align the surface of the silicon oxide layer with the surface of the first silicon nitride layer, wherein the silicon oxide layer remaining in the opening in the first silicon nitride layer forms the insulator;
removing the first silicon nitride layer;
forming a gate layer positioned on a portion of both the surfaces of the p-well and n-well, and a side of the gate layer positioned on the surface of the insulator;
and
performing an ion implantation process to form a doped region positioned on the p-well and a doped region positioned on the n-well, the two doped regions functioning as source and drain of the LD MOS transistor.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/858,519Filed 17 May 2001
Published: 21 Nov 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…
H10D 62/117
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: shapes of semiconductor bodies
H10D 64/516
Characterised by the insulating layers: the thicknesses being non-uniform