CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions
AssigneeInternational Business Machines Corporation
InventorsHeemyong Park, Dominic J. Schepis, Fariborz Assaderaghi
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Abstract
A method is provided for maximizing activation of a gate electrode while preventing source and drain regions from being excessively doped. The gate electrode is partially doped when exposed the source/drain implantation step. Then, the gate electrode is fully doped by the selective implantation step while the source/drain regions are blocked. Separate annealing steps are provided subsequent to the gate doping step and the source and drain implantation step.
Claims22
A method for manufacturing a semiconductor device, comprising the steps of:
- forming a gate electrode on a main surface of a semiconductor substrate with a gate oxide therebetween;
- forming source/drain regions in portions of the main surface adjacent to said gate electrode;
- and
- selectively doping the gate electrode, so that said gate electrode has an impurity concentration higher than that of said source/drain regions.
A semiconductor device comprising:
- a semiconductor substrate;
- a gate oxide formed on a surface of said semiconductor substrate;
- a gate electrode formed on said gate oxide and having a first impurity concentration;
- and
- source/drain regions formed in the surface of said semiconductor substrate and having a second impurity concentration,
- wherein said first impurity concentration of said gate electrode is greater than said second impurity concentration of said source/drain regions.
Dependencies are inferred from the claim text.