Semiconductor integrated device and electronic equipment

A semiconductor integrated device which drives current through first and second signal lines which are terminated at a given impedance Z0 and form a differential pair, the semiconductor integrated device comprising:

• first and second pads through which current is driven exclusively in a signal-output period, the first and second pads being connected to the first and second signal lines, respectively;
• a third pad through which current is driven in a period other than the signal-output period;
• a current source connected between a first power supply and a given node;
• first and second transistors which electrically connect the node with one of the first and second pads in the signal-output period;
• a third transistor which electrically connects the node with the third pad in a period other than the signal-output period;
• a first load element which is connected between a first transmission signal line connecting the first transistor with the first pad and a second power supply, and has an impedance substantially equal to the impedance Z0;
• and
• a second load element which is connected between a second transmission signal line connecting the second transistor with the second pad and a second power supply, and has an impedance substantially equal to the impedance Z0,
• wherein at least one of the first to third transistors is an n-type MOS transistor,
• wherein a signal transmitted through the first and second signal lines is a signal conforming to the Universal Serial Bus (USB) standard,
• wherein the third pad is disposed between the first and second pads,
• wherein the first transistor is inserted between the node and the first pad and has an impedance substantially equal to the impedance Z0/2 when the first transistor is turned on,
• wherein the second transistor is inserted between the node and the second pad and has an impedance substantially equal to the impedance Z0/2 when the second transistor is turned on,
• wherein the third transistor is inserted between the node and the third pad and has an impedance substantially equal to the impedance Z0 when the third transistor is turned on,
• wherein a first cell including the first transistor connected to the first pad and a second cell including the second transistor connected to the second pad are disposed so that parasitic loads on an interconnect and a transistor connected to each of the first and second pads are substantially equal between the first and second cells, and
• wherein the current source is disposed adjacent to the first and second cells.

A semiconductor integrated device which drives current through first and second signal lines which are terminated at a given impedance Z0 and form a differential pair, the semiconductor integrated device comprising:

• first and second pads through which current is driven exclusively in a signal-output period, the first and second pads being connected to the first and second signal lines, respectively;
• a third pad through which current is driven in a period other than the signal-output period;
• a current source connected between a first power supply and a given node;
• first and second transistors which electrically connect the node with one of the first and second pads in the signal-output period;
• a third transistor which electrically connects the node with the third pad in a period other than the signal-output period;
• a first load element which is connected between a first transmission signal line connecting the first transistor with the first pad and a second power supply, and has an impedance substantially equal to the impedance Z0;
• and
• a second load element which is connected between a second transmission signal line connecting the second transistor with the second pad and a second power supply, and has an impedance substantially equal to the impedance Z0;
• and
• a third load element which is connected between the third transistor and the third pad and has an impedance substantially equal to the impedance Z0/2,
• wherein at least one of the first to third transistors is an n-type MOS transistor,
• wherein a signal transmitted through the first and second signal lines is a signal conforming to the Universal Serial Bus (USB) standard,
• wherein the third pad is disposed between the first and second pads,
• wherein the first transistor is inserted between the node and the first pad and has an impedance substantially equal to the impedance Z0/2 when the first transistor is turned on,
• wherein the second transistor is inserted between the node and the second pad and has an impedance substantially equal to the impedance Z0/2 when the second transistor is turned on,
• wherein the third transistor is inserted between the node and the third pad and has an impedance substantially equal to the impedance Z0/2 when the third transistor is turned on,
• wherein a first cell including the first transistor connected to the first pad and a second cell including the second transistor connected to the second pad are disposed so that parasitic loads on an interconnect and a transistor connected to each of the first and second pads are substantially equal between the first and second cells, and
• wherein the current source is disposed adjacent to the first and second cells.

A semiconductor integrated device which drives current through first and second signal lines which are terminated at a given impedance Z0 and form a differential pair, the semiconductor integrated device comprising:

• first and second pads through which current is driven exclusively in a signal-output period, the first and second pads being connected to the first and second signal lines, respectively;
• a third pad through which current is driven in a period other than the signal-output period;
• a current source connected between a first power supply and a given node;
• first and second transistors which electrically connect the node with one of the first and second pads in the signal-output period;
• a third transistor which electrically connects the node with the third pad in a period other than the signal-output period;
• a first load element which is connected between a first transmission signal line connecting the first transistor with the first pad and a second power supply, and has an impedance substantially equal to the impedance Z0;
• and
• a second load element which is connected between a second transmission signal line connecting the second transistor with the second pad and a second power supply, and has an impedance substantially equal to the impedance Z0,
• wherein at least one of the first to third transistors is an n-type MOS transistor,
• wherein a signal transmitted through the first and second signal lines is a signal conforming to the Universal Serial Bus (USB) standard,
• wherein the third pad is disposed between the first and second pads and terminated at an impedance substantially equal to the impedance Z0/2 outside the semiconductor integrated device,
• wherein the first transistor is inserted between the node and the first pad and has an impedance substantially equal to the impedance Z0/2 when the first transistor is turned on,
• wherein the second transistor is inserted between the node and the second pad and has an impedance substantially equal to the impedance Z0/2 when the second transistor is turned on,
• wherein the third transistor is inserted between the node and the third pad and has an impedance substantially equal to the impedance Z0/2 when the third transistor is turned on,
• wherein a first cell including the first transistor connected to the first pad and a second cell including the second transistor connected to the second pad are disposed so that parasitic loads on an interconnect and a transistor connected to each of the first and second pads are substantially equal between the first and second cells, and
• wherein the current source is disposed adjacent to the first and second cells.

A semiconductor integrated device which drives current through first and second signal lines which are terminated at a given impedance Z0 and form a differential pair, the semiconductor integrated device comprising:

• first and second pads through which current is driven exclusively in a signal-output period, the first and second pads being connected to the first and second signal lines, respectively;
• a third pad through which current is driven in a period other than the signal-output period;
• a current source connected between a first power supply and a given node;
• first and second transistors which electrically connect the node with one of the first and second pads in the signal-output period;
• a third transistor which electrically connects the node with the third pad in a period other than the signal-output period;
• a first load element which is connected between a first transmission signal line connecting the first transistor with the first pad and a second power supply, and has an impedance substantially equal to the impedance Z0;
• and
• a second load element which is connected between a second transmission signal line connecting the second transistor with the second pad and a second power supply, and has an impedance substantially equal to the impedance Z0;
• and
• a third load element which is connected between a third transmission signal line connecting the third transistor with the third pad and a second power supply, and has an impedance substantially equal to the impedance Z0,
• wherein at least one of the first to third transistors is an n-type MOS transistor,
• wherein a signal transmitted through the first and second signal lines is a signal conforming to the Universal Serial Bus (USB) standard,
• wherein the third pad is disposed between the first and second pads and terminated at an impedance substantially equal to the impedance Z0 outside the semiconductor integrated device,
• wherein the first transistor is inserted between the node and the first pad and has an impedance substantially equal to the impedance Z0/2 when the first transistor is turned on,
• wherein the second transistor is inserted between the node and the second pad and has an impedance substantially equal to the impedance Z0/2 when the second transistor is turned on,
• wherein the third transistor is inserted between the node and the third pad and has an impedance substantially equal to the impedance Z0/2 when the third transistor is turned on,
• wherein a first cell including the first transistor connected to the first pad and a second cell including the second transistor connected to the second pad are disposed so that parasitic loads on an interconnect and a transistor connected to each of the first and second pads are substantially equal between the first and second cells, and
• wherein the current source is disposed adjacent to the first and second cells.

A semiconductor integrated device which drives current through first and second signal lines which are terminated at a given impedance Z0 and form a differential pair, the semiconductor integrated device comprising:

• first and second pads through which current is driven exclusively in a signal-output period, the first and second pads being connected to the first and second signal lines, respectively;
• a current source connected between a first power supply and a given node;
• first and second transistors which electrically connect the node with one of the first and second pads in the signal-output period;
• a third transistor which electrically connects the node with a second power supply in a period other than the signal-output period;
• a first load element which is connected between a first transmission signal line connecting the first transistor with the first pad and a second power supply, and has an impedance substantially equal to the impedance Z0;
• and
• a second load element which is connected between a second transmission signal line connecting the second transistor with the second pad and a second power supply, and has an impedance substantially equal to the impedance Z0;
• and
• a third load element which is inserted between the third transistor and the second power supply and has an impedance substantially equal to the impedance Z0/2,
• wherein at least one of the first to third transistors is an n-type MOS transistor,
• wherein a signal transmitted through the first and second signal lines is a signal conforming to the Universal Serial Bus (USB) standard,
• wherein the first transistor is inserted between the node and the first pad and has an impedance substantially equal to the impedance Z0/2 when the first transistor is turned on,
• wherein the second transistor is inserted between the node and the second pad and has an impedance substantially equal to the impedance Z0/2 when the second transistor is turned on,
• wherein the third transistor has an impedance substantially equal to the impedance Z0/2 when the third transistor is turned on,
• wherein a first cell including the first transistor connected to the first pad and a second cell including the second transistor connected to the second pad are disposed so that parasitic loads on an interconnect and a transistor connected to each of the first and second pads are substantially equal between the first and second cells, and
• wherein the current source is disposed adjacent to the first and second cells.