Method of forming a MOS transistor on a semiconductor wafer

A method of forming an NMOS transistor, the method comprising:

• providing a silicon substrate with a gate positioned on a surface of the silicon substrate;
• performing a VA ion implantation process with dopants from elements in the VA group to form an n-type doped area in portions of the silicon substrate adjacent to either side of the gate;
• performing a VIIIA/IVA ion implantation process with dopants from the VIIIA or IVA group to form a pocket doped area in portions of the silicon substrate adjacent to portions of the silicon substrate under the n-type doped area;
• depositing a RTCVD dielectric layer that covers both the silicon substrate and the gate;
• etching back the RTCVD dielectric layer to form a spacer on either side of the gate;
• performing a source/drain (S/D) ion implantation process to form an S/D doped area in portions of the silicon substrate adjacent to either side of the gate;
• and
• performing an S/D rapid thermal annealing (RTA) process to activate the dopants implanted into the SID doped area;
• wherein the VIIIA/IVA ion implantation increases concentration uniformity of the dopants in the n-type doped area so as to reduce a substrate current of the NMOS transistor.