Method for forming a flip chip semiconductor package, a semiconductor package formed thereby, and a substrate therefor

A method for forming a flip chip semiconductor package, the method comprising the steps of:

• a) providing a substrate having a first surface with a plurality of raised terminal portions, wherein the plurality of raised terminal portions extend to at least the first surface, each of the raised terminal portions comprising a base portion and a free end portion, at least the free end portions consisting of a first material having a first reflow temperature, wherein the first material is selected from the group consisting of tin-lead eutectic solder and lead-free solder;
• b) providing a semiconductor die having a plurality of pads on a first surface, wherein the plurality of pads have bumps thereon, each of the bumps comprising a base portion and a free end portion, at least the free end portions of the plurality of bumps consisting of the first material;
• c) providing an underfill compound, wherein the underfill compound includes at least some inorganic filler to reduce the coefficient of thermal expansion (CTE) of the underfill compound, wherein the inorganic filler is selected from the group consisting of silica, silicon nitride, boron nitride, and aluminum nitride;
• d) disposing the underfill compound on the substrate;
• e) placing the semiconductor die on the substrate with the underfill compound therebetween, wherein the free end portions of the plurality of bumps abut the free end portions of the plurality of raised terminal portions;
• and
• f) reflowing the semiconductor die, the substrate and the underfill compound at substantially the first reflow temperature to form the at least the free end portions of the plurality of bumps and the at least the free end portions of the plurality of raised terminal portions into interconnects.

A flip chip semiconductor package comprising:

• a substrate having a plurality of raised terminal portions on a first surface and having a plurality of external interconnects;
• a semiconductor die having a plurality of pads on a surface, the semiconductor die being flipped and disposed on the substrate with the first surface of the substrate opposite the surface of the semiconductor die, wherein the semiconductor die has a minimum area of 100 square millimeters;
• a plurality of reflowed conductive interconnects extending between and electrically coupling the plurality of pads to the plurality of terminals;
• and
• underfill compound filling between the first surface of the substrate and the surface of the semiconductor die, wherein the underfill compound includes at least some inorganic filler.

A substrate for a flip chip semiconductor package comprising:

• an electrically non-conductive base layer;
• a patterned layer of electrically conductive material disposed on the non-conductive base layer, the patterned layer of electrically conductive material having terminal locations;
• a patterned layer of an electrically non-conductive material disposed on the patterned layer of electrically conductive material, the patterned layer of electrically non-conductive material having an exposed surface, and the patterned layer of electrically non-conductive material leaving at least some of the terminal locations uncovered;
• and
• raised terminal portions on the terminal locations, wherein the raised terminal portions extend away from the terminal locations to at least the exposed surface of the patterned layer of the electrically nonconductive material.