Phase splitter using digital delay locked loops

A digital phase splitter comprising:

• a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal;
• a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal;
• a third delay line to apply the same amount of delay to a second input clock signal to produce a third output clock signal;
• a fourth delay line connected to the third delay line to apply the same amount of delay to the third output clock signal to produce a fourth output clock signal;
• a feedback path connected to one of the delay lines to produce a feedback signal;
• a phase detector to provide shifting signals based on a difference between phases of the feedback and first input clock signals;
• and
• a controller to adjust the amount of delay applied to all of the delay lines such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are one fourth, one-half, three-fourths and one clock cycle delayed from the first input clock signal.

A digital phase splitter comprising:

• a forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals;
• a feedback path connected to the forward path to produce a feedback signal;
• a phase detector to provide shifting signals based on a difference between the phases of the feedback signal and a second input clock signal;
• and
• a controller to adjust the amount of delay of the forward paths such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.

A digital phase splitter comprising:

• a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal;
• a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal;
• a feedback path connected to the second delay line to produce a feedback signal;
• a phase detector to provide shifting signals based on a difference between phases of the feedback signal and a second input clock signals;
• and
• a controller to adjust the amount of delay applied to the first and second delay lines such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are one-fourth and one-half clock cycle delayed from the first input clock signal.

A digital phase splitter comprising:

• a forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals;
• a feedback path connected to the forward path to produce a feedback signal;
• a first phase detector to provide a first set of shifting signals based on a difference between the phases of the feedback signal and a second input clock signal;
• a second phase detector to provide a second set of shifting signals based on a difference between the phases of the feedback signal and the second input clock signal;
• and
• a controller to adjust the amount of delay of the forward path such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.

A digital phase splitter comprising:

• a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal;
• a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal;
• a feedback path connected to the second delay line to produce a feedback signal;
• a first phase detector to provide a first set of shifting signals based on a difference between the phases of the feedback signal and a second input clock signal;
• a second phase detector to provide a second set of shifting signals based on a difference between the phases of the feedback signal and the second input clock signal;
• and
• a controller to adjust the amount of delay of the forward path such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.

A memory device comprising:

• memory cells;
• a capture circuit;
• and
• a phase splitter connected to provide a clock signal to the capture circuit to capture a data signal from the memory cells, the phase splitter comprising:
• a first forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals;
• a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals;
• a feedback path connected to one of the forward paths to produce a feedback signal;
• a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals;
• and
• a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.

A system comprising:

• a processor;
• a memory device;
• and
• a controller connected between the processor and the memory device, the controller having a phase splitter to generate multiple signals, the phase splitter comprising:
• a first forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals;
• a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals;
• a feedback path connected to one of the forward paths to produce a feedback signal;
• a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals;
• and
• a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.

A method of generating multiple clock signals, the method comprising:

• delaying a first clock signal with an amount of delay to generate first and second output clock signals;
• delaying a second clock signal with the same amount of delay to generate third and fourth output clock signals;
• generating a feedback signal from the fourth output clock signal;
• generating shifting signals based on a difference between the phases of the feedback and first clock signals;
• and
• adjusting the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.

A method of generating multiple clock signals, the method comprising:

• receiving first and second input clock signals;
• propagating the first input clock signal through a number of delay stages of a first delay line to generate a first output clock signal;
• propagating the first output clock signal through the same number of delay stages of a second delay line to generate a second output clock signal;
• propagating the second input clock signal through the same number of delay stages of a third delay line to generate a third output clock signal;
• propagating the third output clock signal through the same number of delay stages of a fourth delay line to generate a fourth output clock signal;
• comparing a phase difference between the fourth output clock and first input clock signals to determine to provide shifting signals;
• adjusting the amount of delay based on the shifting signals such that when the fourth output clock and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.

A method of generating multiple clock signals, the method comprising:

• delaying a first input clock signal to generate a first output clock signal;
• delaying the first output clock signal to generate a second output clock signal;
• generating a feedback signal from the second output clock signal;
• synchronizing the feedback and the second input clock signals such that the first, second output clock signals are one-fourth and one-half clock cycle delayed from the first input clock signal.

A method of generating multiple clock signals, the method comprising:

• delaying a first input clock signal to generate a first output clock signal;
• delaying the first output clock signal to generate a second output clock signal;
• delaying a second clock signal to generate a third output clock signal;
• delaying the third output clock signal to generate a fourth output clock signal;
• generating a feedback signal from the fourth output clock signal;
• synchronizing the feedback and the second input clock signals such that the first, second, third and fourth output clock signals are one-fourth, one-half three-fourths and one clock cycle delayed from the first input clock signal.