Large-input-delay variation tolerant (lidvt) receiver adopting FIFO mechanism
AssigneeSilicon Integrated Systems Corp.
InventorsYi-Hung Chen, Ming-Shien Lee, Jew-Yong Kuo
Life of this patent
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Abstract
The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.
Claims8
A circuit for receiving input data with a delay variation, the input data including multiple units of data input to the circuit in a predetermined sequence, comprising:
- a write-enable pulse sequencer, in response to a reset signal and a clock signal, for sequentially generating a plurality of write-enable signals;
- an N-stage register including N stages of register, the N-stage register, in response to the plurality of write-enable signals, for sequentially storing each of multiple units of data within one corresponding stage of register, each of N stages of register having an output terminal outputting one corresponding unit of data;
- an output stage selector for generating a control signal;
- and
- a multiplexer inputting each one corresponding unit of data from the N-stage register, the multiplexer, responsive to the control signal, for outputting each one corresponding unit of data according to said predetermined sequence.
Dependencies are inferred from the claim text.