Method and apparatus for calibrating an IEEE-1394 cycle master
AssigneeApple Computer, Inc.
InventorErik P. Staats
Life of this patent
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Abstract
A cycle master in a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus is calibrated by first computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and then adjusting a frame rate of said packet arrival events to compensate for said clock offset.
Claims9
A method of calibrating a cycle master in a digital network, comprising the steps of:
- computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events;
- and
- adjusting a frame rate of said packet arrival events to compensate for said clock offset.
A host controller for a digital sytem comprising a calibration cycle time register configured to store time values synchronized to periodic ones of a plurality of packet arrival events.
A method comprising:
- measuring an accuracy of a cycle timer in a digital network;
- and
- adjusting a frame rate of data transmitted within the digital network according to the accuracy of the cycle timer.
Dependencies are inferred from the claim text.