Clock signal decoupling for synchronous operation
AssigneeIntel Corporation
InventorsOon-Sim Ang, Barry Kazuto Tsuji, Oreste Basil Varelas
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsOon-Sim Ang, Barry Kazuto Tsuji, Oreste Basil Varelas
Estimating the term…
Method and apparatus is described for decoupling data from a clock signal and recoupling the data to a different clock signal for subsequent synchronous processing by a pointer processor. More particularly, on a receive or drop side, one buffer is configured to store payload pointers and a synchronous payload envelope arriving clocked by a line clock signal, while another buffer is configure to store TOH or SOH arriving clocked by the line clock signal. Each buffer clocks out such stored information off of a same system clock signal, such as a drop clock signal. On a transmit or add side, a buffer is configured to store payload pointers and a synchronous payload envelope. This buffer clocks in such stored information off of a system clock signal, such as an add clock signal, and clocks out such stored information off of a transmit reference clock signal. Output of such buffers, whether on a drop or add side, is provided to a pointer processor buffer, where both an input side and an output side of the pointer processor buffer are operated off of a system clock signal or a signal synchronized with the system clock signal.
A temporary storage device, comprising:
The temporary storage device of claim 9 wherein the first portion of the information or the second portion of the information is tagged with an H1-pointer byte.
A network node comprising:
A network node comprising:
A network comprising:
A method for avoiding one or more asynchronicities in pointer processing, comprising:
A network comprising:
A temporary storage device configured to receive overhead information and data, comprising:
Dependencies are inferred from the claim text.