Apparatus amd method for disparate fabric data and transaction buffering within infiniband device

A transaction switch for switching data between a plurality of data devices, comprising:

• a memory, shared by the plurality of data devices for buffering data received thereby;
• multiplexing logic, for controlling the transfer of data between the plurality of data devices and said memory;
• and
• control logic, for controlling said multiplexing logic;
• wherein the plurality of data devices comprise a plurality of packetized data devices and a plurality of addressed data devices;
• wherein said control logic is configured to selectively control said multiplexing logic to transfer data through said memory between two of said packetized data devices and between one of said packetized data devices and one of said addressed data devices.

A transaction switch for switching transactions and data between a plurality of data interfaces, the transaction switch comprising:

• a memory, shared by the plurality of data interfaces, for buffering data received thereby;
• a plurality of transaction queues, associated with each of the plurality of data interfaces, configured to store transactions, said transactions adapted to convey information to enable the plurality of data interfaces to transfer said data according to a plurality of disparate data transfer protocols supported thereby;
• and
• control logic, configured to route said data through said shared memory between the plurality of data interfaces and to switch said transactions between the plurality of data interfaces.

An integrated circuit, comprising:

• at least three data interfaces;
• a memory, shared by said at least three data interfaces for buffering data therebetween;
• and
• a transaction switch, coupled to said at least three data interfaces and said memory, for dynamically allocating portions of said memory to said at least three data interfaces for storing data therein, and for controlling access to said allocated portions of said memory by each of said at least three data interfaces;
• wherein at least one of said at least three data interfaces is of a different type than the others.

An integrated circuit, comprising:

• a plurality of packetized data interfaces;
• a plurality of addressed data interfaces;
• and
• a transaction switch, coupled to said plurality of packetized data interfaces and to said plurality of addressed data interfaces;
• wherein said transaction switch is configured to switch a packetized data transaction from a first of said plurality of packetized data interfaces to a second of said plurality of packetized data interfaces and to switch an addressed data transaction from a first of said addressed data interfaces to a second of said addressed data interfaces.

An InfiniBand hybrid channel adapter/switch, comprising:

• a plurality of InfiniBand ports;
• at least one addressed data bus interface;
• a memory, for buffering data received by said plurality of InfiniBand ports and said at least one addressed data bus interface;
• a transport layer engine for routing said data between said plurality of InfiniBand ports and said at least one addressed data bus interface;
• a plurality of transaction queues, associated with each of said plurality of InfiniBand ports, said at least one addressed data bus interface and said transport layer engine, for storing transactions;
• and
• a transaction switch, coupled to said plurality of transaction queues, configured to route said transactions between said plurality of InfiniBand ports, said at least one addressed data bus interface and said transport layer engine.

A transaction switch in a network device having a buffer memory and plurality of data devices, including packetized and addressed data devices, the transaction switch comprising:

• a buffer manager, for allocating portions of the buffer memory to the plurality of data devices on an as-needed basis;
• a plurality of data paths, for providing the plurality of data devices access to the buffer memory;
• a mapping table, for storing packet destination identification information;
• a plurality of transaction queues, for transferring transactions between the transaction switch and the plurality of data devices;
• and
• control logic, for selectively switching data between the plurality of data devices based on said mapping table information and in response to said transactions.