Dram technology compatible processor/memory chips

A programmable logic array, comprising:

• a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
• a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
• and
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor (MOSFET);
• a stacked capacitor formed according to a dynamic random access memory (DRAM) process;
• and
• an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

An address decoder for a memory device, the address decoder comprising:

• a number of address lines;
• a number of output lines;
• wherein the address lines, and the output lines form an array;
• a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET;
• and
• wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines.

An electronic system, comprising:

• a memory;
• and
• a processor coupled to the memory and formed on a die common with the memory;
• and
• wherein the processor includes at least one programmable logic array including:
• a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor (MOSFET);
• a stacked capacitor formed according to a dynamic random access memory (DRAM) process;
• and
• an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

• a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer;
• a plurality of stacked capacitors disposed above the plurality of MOSFETs and separated from the plurality of MOSFETs by an insulator layer;
• and
• wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;
• wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit;
• and
• wherein the first sub-circuit is operatively coupled to the second sub-circuit.

An integrated circuit, comprising:

• a processor;
• a memory, operatively coupled to the processor;
• and
• wherein the processor and the memory are formed on the same semiconductor substrate and the processor includes at least one programmable logic array with a non-volatile memory cell that includes a metal oxide semiconductor field effect transistor with a stacked capacitor coupled to its gate.

A method for forming an integrated circuit, the method comprising:

• forming a plurality of metal oxide semiconductor transistors (MOSFETs) in and on a layer of semiconductor material;
• forming a first set of stacked capacitors that are coupled to diffusion regions of selected ones of the plurality of MOSFETs to form a memory array;
• and
• forming, on the same layer of semiconductor material, a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a plurality of non-volatile memory cells;
• and
• interconnecting the memory array and the non-volatile memory cells to provide the integrated circuit.

An electronic system, comprising:

• a memory;
• and
• a processor coupled to the memory and formed on a die common with the memory;
• and
• wherein the processor includes at least one programmable logic array including:
• a logic plane that receives a number of input signals, the logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor;
• a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to a gate of the transistor.

An electronic system, comprising:

• a memory;
• and
• a processor coupled to the memory and formed on a die common with the memory;
• and
• wherein the die includes at least one programmable logic array including:
• a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile first memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
• and
• a second logic plane having a number of non-volatile second memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,
• wherein the first non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor;
• a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0;
• and
• an electrical contact that couples the stacked capacitor to a gate of the transistor.

An electronic system, comprising:

• a memory;
• and
• a processor coupled to the memory and formed on a die common with the memory;
• and
• wherein the processor includes at least one programmable logic array including:
• a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and
• wherein the non-volatile memory cells each include:
• a metal oxide semiconductor field effect transistor (MOSFET) having a gate oxide, wherein the gate oxide has a thickness of less than 100 angstroms;
• a stacked capacitor formed according to a dynamic random access memory (DRAM) process;
• and
• an electrical contact that couples the stacked capacitor to a gate of the MOSFET.