Integrated memory
AssigneeInfineon Technologies AG
InventorRobert Feurle
Life of this patent
Estimating the term…
Abstract
An integrated memory having a memory cell array has a control circuit for controlling a memory access for reading out or writing a data signal of one of the memory cells. The control circuit receives, for a memory access, an access command in the form of an activation command, a read command or a write command. Furthermore, the control circuit is designed and can be operated in such a way that, for a memory access, a configuration value for a CAS latency and/or a configuration value for specifying a burst access is received in a combined manner with the access command. As a result, a mode register and a corresponding programming step for programming the register can be eliminated.
Claims7
An integrated memory, comprising:
- a memory cell array having memory cells;
- and
- a control circuit for controlling a memory access selected from the group consisting of a read memory access for reading out a data signal from one of said memory cells and a write memory access for writing a data signal into one of said memory cells;
- for performing the memory access, said control circuit designed for receiving an access command selected from the group consisting of an activation command, a read command, and a write command;
- for performing the memory access, said control circuit designed for receiving a configuration value in a combined manner with the access command;
- and
- the configuration value being selected from the group consisting of a CAS latency value and a value for specifying a burst access.
Dependencies are inferred from the claim text.