Column repair circuit of semiconductor memory
AssigneeHynix Semiconductor Inc.
InventorHyung Dong Lee
Life of this patent
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Abstract
A column repair circuit of a semiconductor memory is disclosed, in which a column repair efficiency is increased in a row flexible redundancy structure. A repair circuit for a memory divided into arrays and arranged by row lines and column lines crossing each other, the circuit includes a plurality of column fuse boxes for outputting a redundant column enable signal for repairing a defective line, and an array address inverter corresponding to one of the column fuse boxes for inverting a self-pair signal input thereto and a corresponding array address input thereto, the self-pair signal indicating whether a row repair is performed in a corresponding array or in another array, and for selectively outputting the inverted array address according to the self-pair signal.
Claims18
A repair circuit for a memory divided into arrays and arranged by row lines and column lines crossing each other, the circuit comprising:
- a plurality of column fuse boxes for outputting a redundant column enable signal for repairing a defective line;
- and
- an array address inverter corresponding to one of the column fuse boxes for inverting a self-pair signal input thereto and a corresponding array address input thereto, and for selectively outputting the inverted array address according to the self-pair signal, the self-pair signal indicating whether a row repair is performed in a corresponding array or in another array.
A repair circuit for a memory, comprising:
- a plurality of column fuse boxes for outputting a redundant column enable signal for repairing a defective line, each of the column fuse boxes including,
- an array address fuse and latch box for latching a fuse based on a row cycle timing signal and a coded array address, and
- a column address fuse box for outputting a column redundant signal based on an output signal from the array address fuse and latch box, an externally input column cycle timing signal and a column address;
- a plurality of array address inverters each corresponding to one of the column fuse boxes, each of the array address inverters inverting a self-pair signal input thereto and a corresponding array address input thereto, and selectively outputting the inverted array address as part of the coded array address according to the self-repair signal, the self-pair signal indicating whether a row repair is performed in a corresponding array or in another array;
- and
- a column enable signal outputting unit for processing the column redundant signals from the column address fuse boxes and thereby outputting the redundant column enable signal.
A device for repairing a memory, the device comprising:
- a plurality of fuse sections for outputting a redundant line enable signal for repairing a defective area of the memory;
- and
- at least one array address inverter corresponding to one of the fuse sections, the array address inverter inverting a self-pair signal input thereto and a corresponding array address input thereto and selectively outputting the inverted array address to the corresponding one of the fuse sections.
Dependencies are inferred from the claim text.