Column decoder with increased immunity to high voltage breakdown
AssigneeWinbond Electronics Corp.
InventorChang Wan Ha
Life of this patent
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Abstract
A column decoder in an electrically-erasable, programmable read-only memory applies a bias voltage to, or floats, the gates of selected transistors during an erasure operation. This reduces the potential for gate oxide breakdown by decreasing the voltage difference between the gate and the relatively high erasure voltage. This allows the use of transistors having a thinner gate oxide, enabling easier laying out of the transistors within a given bit line pitch.
Claims12
An electrically-erasable, programmable read-only memory, comprising:
- a plurality of bit lines;
- a plurality of source lines;
- a plurality of cell transistors coupling the bit lines and the source lines;
- a plurality of bit line discharge transistors coupled to selectively discharge said plurality of bit lines;
- a plurality of bit line selection transistors coupled to select said plurality of bit lines;
- and
- a plurality of column decoder circuits coupled to selectively decode values l stored by said plurality of cell transistors,
- wherein said plurality of column decoder circuits is further coupled to provide, during an erasure operation, a bias voltage to at least one of said plurality of bit line discharge transistors and of said plurality of bit line selection transistors.
An electrically-erasable, programmable read-only memory, comprising:
- a plurality of bit lines;
- a plurality of source lines;
- a plurality of cell transistors coupling the bit lines and the source lines;
- a plurality of bit line discharge transistors coupled to selectively discharge said plurality of bit lines;
- a plurality of bit line selection transistors coupled to select said plurality of bit lines;
- and
- a plurality of column decoder circuits coupled to selectively decode values stored by said plurality of cell transistors,
- wherein said plurality of column decoder circuits is further coupled to float, during an erasure operation, at least one of said plurality of bit line discharge transistors and of said plurality of bit line selection transistors.
A method of reducing gate oxide breakdown in at least one of a bit line discharging transistor and a bit line selection transistor in an electrically-erasable, programmable read-only memory, comprising the acts of:
- receiving an erasure signal;
- and
- providing a bias voltage to a gate of said at least one transistor in accordance with the erasure signal.
A method of reducing gate oxide breakdown in at least one of a bit line discharging transistor and a bit line selection transistor in an electrically-erasable, programmable read-only memory, comprising the acts of:
- receiving an erasure signal;
- and
- floating a gate of said at least one transistor in accordance with the erasure signal.
Dependencies are inferred from the claim text.