Integrated circuit having an EEPROM and flash EPROM using a memory cell with source-side programming

A method of operating a non-volatile integrated circuit memory having an EEPROM array and a flash EPROM array, the method comprising:

• accessing a memory cell in the EEPROM array having a plurality of memory cells arranged along rows and columns, each memory cell having a drain region, a source region, a gate terminal, a floating gate, and a channel region between its source and drain regions, the EEPROM array further having a plurality of data lines each being coupled to a drain region of each of a plurality of memory cells along a column, and a plurality of source lines each being coupled to a source region of each of a plurality of memory cells along a row;
• and
• providing a voltage representing the data to be programmed in the accessed memory cell on a preselected data line coupled to the accessed cell, wherein a threshold voltage of the accessed memory cell is increased by injection of hot electrons from a portion of the selected cell's channel region substantially near the source region to the accessed cell's floating gate.