Dirty tag bits for 3D-RAM SRAM

A graphics system comprising:

• a memory array configured to receive and store graphics data, wherein the memory array comprises:
• a plurality of DRAM banks, wherein each DRAM bank is logically subdivided into pages, and wherein each page is further subdivided into blocks,
• a plurality of level two write-through caches connected to the DRAM banks, wherein the number of level two caches is equal to the number of DRAM banks, and wherein the storage capacity of the level two caches is equal to a page,
• a level one write-back cache connected to the level two caches and configured to receive and store a plurality of graphics data blocks;
• an array of memory circuits configured to store the status of the graphics data stored in the level one cache, wherein the status indicates whether the graphics data is modified or unmodified;
• and
• a cache controller connected to the level two caches, the level one cache, and the array of memory circuits, wherein the cache controller is configured to control the transfer of graphics data between the caches according to the contents of the memory circuits.

A method for storing pixel data in a memory array, wherein the method comprises:

• a) arithmetically combining pixel data with the contents of a temporary storage space, wherein the result is stored in the temporary storage space;
• b) maintaining an array of status bits indicative of whether or not data stored in the temporary storage space has been modified;
• c) periodically determining if any of the status bits indicate that the corresponding data within a block of temporary storage space has been modified;
• d) issuing a request to write a block of data to the memory array if the corresponding status bits indicate that the data has been modified;
• e) copying only the modified data from the temporary storage space to the memory array;
• and
• f) changing the state of the status bits corresponding to the block of data written to the memory array to indicate the associated data is unmodified.

A method for externally managing cached pixel data within a 3D-RAM memory device, the method comprising:

• identifying a block within a level one cache, wherein the block is either a target or a source for a data block transfer with a level two cache;
• maintaining status bits for each data block in the level one cache;
• setting one or more of the status bits to a known state in response to a data block transfer, wherein the known state indicates that the data within the block of level one cache is unmodified;
• and
• identifying write operations to the level one cache, wherein the source of the write data is external to the 3D-RAM;
• setting the status bit associated with the data value in the level one cache to a known state in response to a write operation, wherein the known state indicates the data within the level one cache is modified;
• and synchronizing the data in the level two cache to the data in the level one cache according to the state information stored in the status bits.

A method for reducing the power consumption in a 3D-RAM, the method comprising:

• associating dirty tag bits with pixels stored in a level one cache, wherein the dirty tag bits are external to the 3D-RAM, wherein the state of the dirty tag bits indicate that the associated pixel is dirty if the pixel has been modified or clean if the pixel has not been modified;
• grouping the dirty tag bits into status words, wherein a status word is associated with one and only one block of the level one cache memory;
• and
• writing-back blocks of pixel data within the level one cache to a level two cache according to the contents of the status words, wherein only dirty pixels are written-back.