Scalable unified memory architecture
AssigneeRambus Inc.
InventorRichard E. Perego
Life of this patent
Estimating the term…
Abstract
A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.
Claims34
An apparatus comprising:
- a memory controller;
- and
- at least one module coupled to the memory controller, each module including:
- a computing engine configured to receive information from the memory controller;
- and
- a shared memory coupled to the computing engine, wherein the shared memory includes storage for data which includes a portion of the main memory for a central processing unit (CPU).
An apparatus comprising:
- a memory controller;
- a plurality of memory modules coupled to the memory controller, each module including:
- a rendering engine configured to receive data to be processed from the memory controller;
- and
- a shared memory coupled to the rendering engine, wherein the shared memory includes storage for a portion of the main memory for a central processing unit (CPU) coupled to the memory controller.
A module comprising:
- a rendering engine configured to receive information from a memory controller;
- and
- a shared memory coupled to the rendering engine, wherein the shared memory is configured to store main memory data as well as graphical data, wherein the module is configured to be coupled to or decoupled from the memory controller.
A method comprising:
- receiving a processing task at a memory controller;
- partitioning the processing task into a plurality of portions;
- and
- distributing each portion of the processing task to one of a plurality of computing engines, wherein each of the plurality of computing engines is coupled between the memory controller and a shared memory associated with the computing engine, and wherein the shared memory includes storage for a portion of the main memory for a central processing unit (CPU).
Dependencies are inferred from the claim text.